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1; RUN: llc -mtriple=hexagon -hexagon-expand-condsets=0 -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s2;3; Expand-condsets eliminates the "mux" instruction, which is what this4; testcase is checking.5 6; Test that we don't generate a new value compare if the operands are7; the same register.8 9; CHECK-NOT: cmp.eq([[REG0:(r[0-9]+)]].new,[[REG0]])10; CHECK: cmp.eq([[REG1:(r[0-9]+)]],[[REG1]])11 12%s.0 = type { i16, i8, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, [2 x i32], ptr, ptr, ptr, %s.1, ptr, [8 x i8], i8 }13%s.1 = type { i32, i16, i16 }14 15@g0 = external global %s.016@g1 = external unnamed_addr constant [23 x i8], align 817 18; Function Attrs: nounwind19declare void @f0(ptr nocapture, ptr nocapture readonly, ...) #020 21define void @f1() #1 {22b0:23 %v0 = load ptr, ptr undef, align 424 %v1 = load i32, ptr undef, align 425 br i1 undef, label %b4, label %b126 27b1: ; preds = %b028 %v2 = icmp slt i32 %v1, 029 %v3 = lshr i32 %v1, 530 %v4 = add i32 %v3, -13421772831 %v5 = select i1 %v2, i32 %v4, i32 %v332 %v6 = getelementptr inbounds i32, ptr %v0, i32 %v533 %v7 = icmp ult ptr %v6, %v034 %v8 = select i1 %v7, i32 0, i32 135 br i1 undef, label %b2, label %b436 37b2: ; preds = %b138 %v9 = icmp slt i32 %v1, 039 %v10 = lshr i32 %v1, 540 %v11 = add i32 %v10, -13421772841 %v12 = select i1 %v9, i32 %v11, i32 %v1042 %v13 = getelementptr inbounds i32, ptr %v0, i32 %v1243 %v14 = icmp ult ptr %v13, %v044 %v15 = select i1 %v14, i32 0, i32 145 %v16 = icmp eq i32 %v8, %v1546 br i1 %v16, label %b4, label %b347 48b3: ; preds = %b249 call void (ptr, ptr, ...) @f0(ptr @g0, ptr @g1, i32 %v8, i32 %v15) #050 unreachable51 52b4: ; preds = %b2, %b1, %b053 br i1 undef, label %b6, label %b554 55b5: ; preds = %b456 unreachable57 58b6: ; preds = %b459 ret void60}61 62attributes #0 = { nounwind "target-cpu"="hexagonv5" }63attributes #1 = { "target-cpu"="hexagonv5" }64