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1; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 -disable-hexagon-misched < %s \2; RUN: | FileCheck %s3; Check that we generate new value jump, both registers, with one4; of the registers as new.5 6@Reg = common global i32 0, align 47define i32 @main() nounwind {8entry:9; CHECK: if (cmp.gt(r{{[0-9]+}}.new,r{{[0-9]+}})) jump:{{[t|nt]}} .LBB{{[0-9]+}}_{{[0-9]+}}10 %Reg2 = alloca i32, align 411 %0 = load i32, ptr %Reg2, align 412 %1 = load i32, ptr @Reg, align 413 %tobool = icmp sle i32 %0, %114 br i1 %tobool, label %if.then, label %if.else15 16if.then:17 call void @bar(i32 1, i32 2)18 br label %if.end19 20if.else:21 call void @baz(i32 10, i32 20)22 br label %if.end23 24if.end:25 ret i32 026}27 28declare void @bar(i32, i32)29declare void @baz(i32, i32)30