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1; RUN: llc -mtriple=hexagon < %s2; REQUIRES: asserts3 4; Splitting live ranges of vector predicate registers (in hexagon-peephole)5; moved a PHI instruction into the middle of another basic block causing a6; crash later on. Make sure this does not happen and that the testcase7; compiles successfully.8 9target triple = "hexagon"10 11; Function Attrs: nounwind12define void @f0() local_unnamed_addr #0 {13b0:14 %v0 = icmp eq i32 undef, 015 br i1 %v0, label %b1, label %b216 17b1: ; preds = %b018 %v1 = tail call <128 x i1> @llvm.hexagon.V6.pred.not.128B(<128 x i1> undef) #219 br label %b220 21b2: ; preds = %b1, %b022 %v2 = phi <128 x i1> [ %v1, %b1 ], [ undef, %b0 ]23 br label %b324 25b3: ; preds = %b3, %b226 %v3 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<128 x i1> %v2, <32 x i32> undef, <32 x i32> undef) #227 %v4 = tail call <32 x i32> @llvm.hexagon.V6.vor.128B(<32 x i32> undef, <32 x i32> %v3) #228 %v5 = tail call <32 x i32> @llvm.hexagon.V6.vor.128B(<32 x i32> %v4, <32 x i32> undef) #229 %v6 = tail call <128 x i1> @llvm.hexagon.V6.vgtub.128B(<32 x i32> %v5, <32 x i32> undef) #230 %v7 = tail call <128 x i1> @llvm.hexagon.V6.pred.or.128B(<128 x i1> %v6, <128 x i1> undef) #231 %v8 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<128 x i1> %v7, <32 x i32> undef, <32 x i32> undef) #232 tail call void asm sideeffect "if($0) vmem($1)=$2;", "q,r,v,~{memory}"(<128 x i1> undef, ptr undef, <32 x i32> %v8) #233 br label %b334}35 36; Function Attrs: nounwind readnone37declare <32 x i32> @llvm.hexagon.V6.vmux.128B(<128 x i1>, <32 x i32>, <32 x i32>) #138 39; Function Attrs: nounwind readnone40declare <128 x i1> @llvm.hexagon.V6.vgtub.128B(<32 x i32>, <32 x i32>) #141 42; Function Attrs: nounwind readnone43declare <128 x i1> @llvm.hexagon.V6.pred.or.128B(<128 x i1>, <128 x i1>) #144 45; Function Attrs: nounwind readnone46declare <128 x i1> @llvm.hexagon.V6.pred.not.128B(<128 x i1>) #147 48; Function Attrs: nounwind readnone49declare <32 x i32> @llvm.hexagon.V6.vor.128B(<32 x i32>, <32 x i32>) #150 51attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }52attributes #1 = { nounwind readnone }53attributes #2 = { nounwind }54