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1# RUN: llc < %s -x mir -mtriple=hexagon -run-pass=modulo-schedule-test -pipeliner-experimental-cg=true | FileCheck %s2 3# Simple check for this basic correctness test; ensure all instructions are in stage 0 in4# the prolog and stage 3 in the epilog.5 6# CHECK-NOT: Stage-37# CHECK: J2_loop0r8# CHECK: intregs = S2_addasl_rrri %{{[0-9]+}}, %{{[0-9]+}}, 1, post-instr-symbol <mcsymbol Stage-0_Cycle-0>9# CHECK: intregs = L2_loadruh_io %{{[0-9]+}}, -4, post-instr-symbol <mcsymbol Stage-3_Cycle-0> :: (load (s16) from %ir.cgep2, !tbaa !0)10# CHECK: intregs = S2_storerh_pi %{{[0-9]+}}, -2, %{{[0-9]+}}, post-instr-symbol <mcsymbol Stage-3_Cycle-0> :: (store (s16) into %ir.lsr.iv, !tbaa !0)11# CHECK: intregs = nsw A2_addi %{{[0-9]+}}, -1, post-instr-symbol <mcsymbol Stage-0_Cycle-0>12# CHECK: ENDLOOP0 %bb.{{[0-9]+}}, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc013# CHECK-NOT: Stage-014 15--- |16 ; ModuleID = '/google/src/cloud/jmolloy/tc/google3/third_party/llvm/llvm/test/CodeGen/Hexagon/swp-phi-start.ll'17 source_filename = "/google/src/cloud/jmolloy/tc/google3/third_party/llvm/llvm/test/CodeGen/Hexagon/swp-phi-start.ll"18 target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"19 20 ; Function Attrs: nounwind21 define void @f0(i32 %a0, ptr nocapture %a1) #0 {22 b0:23 br i1 undef, label %b1, label %b2.preheader24 25 b1: ; preds = %b026 br i1 undef, label %b3, label %b2.preheader27 28 b2.preheader: ; preds = %b0, %b129 %cgep = getelementptr i16, ptr %a1, i32 undef30 br label %b231 32 b2: ; preds = %b2.preheader, %b233 %lsr.iv = phi ptr [ %cgep, %b2.preheader ], [ %cgep3, %b2 ]34 %v1 = phi i32 [ %v7, %b2 ], [ undef, %b2.preheader ]35 %v2 = phi i32 [ %v1, %b2 ], [ %a0, %b2.preheader ]36 %v3 = add nsw i32 %v2, -237 %cgep2 = getelementptr inbounds i16, ptr %a1, i32 %v338 %v5 = load i16, ptr %cgep2, align 2, !tbaa !039 store i16 %v5, ptr %lsr.iv, align 2, !tbaa !040 %v7 = add nsw i32 %v1, -141 %v8 = icmp sgt i32 %v7, 042 %cgep3 = getelementptr i16, ptr %lsr.iv, i32 -143 br i1 %v8, label %b2, label %b344 45 b3: ; preds = %b2, %b146 ret void47 }48 49 attributes #0 = { nounwind "target-cpu"="hexagonv55" }50 51 !0 = !{!1, !1, i64 0}52 !1 = !{!"short", !2, i64 0}53 !2 = !{!"omnipotent char", !3, i64 0}54 !3 = !{!"Simple C/C++ TBAA"}55 56...57---58name: f059alignment: 1660exposesReturnsTwice: false61legalized: false62regBankSelected: false63selected: false64failedISel: false65tracksRegLiveness: true66hasWinCFI: false67registers:68 - { id: 0, class: intregs, preferred-register: '' }69 - { id: 1, class: intregs, preferred-register: '' }70 - { id: 2, class: intregs, preferred-register: '' }71 - { id: 3, class: intregs, preferred-register: '' }72 - { id: 4, class: intregs, preferred-register: '' }73 - { id: 5, class: intregs, preferred-register: '' }74 - { id: 6, class: intregs, preferred-register: '' }75 - { id: 7, class: intregs, preferred-register: '' }76 - { id: 8, class: predregs, preferred-register: '' }77 - { id: 9, class: predregs, preferred-register: '' }78 - { id: 10, class: intregs, preferred-register: '' }79 - { id: 11, class: intregs, preferred-register: '' }80 - { id: 12, class: intregs, preferred-register: '' }81 - { id: 13, class: predregs, preferred-register: '' }82 - { id: 14, class: intregs, preferred-register: '' }83liveins:84 - { reg: '$r0', virtual-reg: '%6' }85 - { reg: '$r1', virtual-reg: '%7' }86frameInfo:87 isFrameAddressTaken: false88 isReturnAddressTaken: false89 hasStackMap: false90 hasPatchPoint: false91 stackSize: 092 offsetAdjustment: 093 maxAlignment: 194 adjustsStack: false95 hasCalls: false96 stackProtector: ''97 maxCallFrameSize: 429496729598 cvBytesOfCalleeSavedRegisters: 099 hasOpaqueSPAdjustment: false100 hasVAStart: false101 hasMustTailInVarArgFunc: false102 localFrameSize: 0103 savePoint: []104 restorePoint: []105fixedStack: []106stack: []107callSites: []108constants: []109machineFunctionInfo: {}110body: |111 bb.0.b0:112 successors: %bb.1(0x40000000), %bb.2(0x40000000)113 liveins: $r0, $r1114 115 %7:intregs = COPY $r1116 %6:intregs = COPY $r0117 %8:predregs = IMPLICIT_DEF118 J2_jumpt %8, %bb.2, implicit-def dead $pc119 J2_jump %bb.1, implicit-def dead $pc120 121 bb.1.b1:122 successors: %bb.4(0x40000000), %bb.2(0x40000000)123 124 %9:predregs = IMPLICIT_DEF125 J2_jumpt %9, %bb.4, implicit-def dead $pc126 J2_jump %bb.2, implicit-def dead $pc127 128 bb.2.b2.preheader:129 successors: %bb.3(0x80000000)130 131 %10:intregs = IMPLICIT_DEF132 %14:intregs = COPY %10133 J2_loop0r %bb.3, %14, implicit-def $lc0, implicit-def $sa0, implicit-def $usr134 135 bb.3.b2 (machine-block-address-taken):136 successors: %bb.3(0x7c000000), %bb.4(0x04000000)137 138 %1:intregs = PHI %7, %bb.2, %5, %bb.3, post-instr-symbol <mcsymbol Stage-3_Cycle-0>139 %2:intregs = PHI %10, %bb.2, %4, %bb.3, post-instr-symbol <mcsymbol Stage-0_Cycle-0>140 %3:intregs = PHI %6, %bb.2, %2, %bb.3, post-instr-symbol <mcsymbol Stage-0_Cycle-0>141 %11:intregs = S2_addasl_rrri %7, %3, 1, post-instr-symbol <mcsymbol Stage-0_Cycle-0>142 %12:intregs = L2_loadruh_io %11, -4, post-instr-symbol <mcsymbol Stage-3_Cycle-0> :: (load (s16) from %ir.cgep2, !tbaa !0)143 %5:intregs = S2_storerh_pi %1, -2, %12, post-instr-symbol <mcsymbol Stage-3_Cycle-0> :: (store (s16) into %ir.lsr.iv, !tbaa !0)144 %4:intregs = nsw A2_addi %2, -1, post-instr-symbol <mcsymbol Stage-0_Cycle-0>145 ENDLOOP0 %bb.3, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0146 J2_jump %bb.4, implicit-def dead $pc147 148 bb.4.b3:149 PS_jmpret $r31, implicit-def dead $pc150 151...152