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1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2 3; Check that post-increment store instructions are being generated.4; CHECK: memw(r{{[0-9]+}}++#4) = r{{[0-9]+}}5 6define i32 @f0(ptr nocapture %a0, ptr nocapture %a1, i32 %a2) #0 {7b0:8 br label %b19 10b1: ; preds = %b1, %b011 %v0 = phi i32 [ %v10, %b1 ], [ 10, %b0 ]12 %v1 = phi ptr [ %a0, %b0 ], [ %v8, %b1 ]13 %v2 = phi ptr [ %a1, %b0 ], [ %v9, %b1 ]14 %v3 = load i32, ptr %v1, align 415 %v4 = load i16, ptr %v2, align 216 %v5 = sext i16 %v4 to i3217 %v6 = mul i32 %v3, 218 %v7 = add i32 %v6, %v519 store i32 %v7, ptr %v1, align 420 %v8 = getelementptr i32, ptr %v1, i32 121 %v9 = getelementptr i16, ptr %v2, i32 122 %v10 = add i32 %v0, -123 %v11 = icmp eq i32 %v10, 024 br i1 %v11, label %b2, label %b125 26b2: ; preds = %b127 ret i32 028}29 30attributes #0 = { nounwind "target-cpu"="hexagonv5" }31