81 lines · plain
1; RUN: llc -O2 -mtriple=hexagon < %s | FileCheck %s2; Rely on the comments generated by llc. Check that "if.then" was not predicated.3; CHECK: b54; CHECK: b25; CHECK-NOT: if{{.*}}memd6 7%s.0 = type { [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [3 x i32], [24 x i32], [8 x %s.1], [5 x i32] }8%s.1 = type { i32, i32 }9 10@g0 = global i64 011@g1 = global i32 012@g2 = global i32 013@g3 = global i8 014 15declare i32 @llvm.hexagon.S2.cl0(i32) #016declare i32 @llvm.hexagon.S2.setbit.r(i32, i32) #017declare i64 @llvm.hexagon.M2.vmpy2s.s0(i32, i32) #018declare i64 @llvm.hexagon.M2.vmac2s.s0(i64, i32, i32) #019declare i64 @llvm.hexagon.A2.vaddws(i64, i64) #020declare i64 @llvm.hexagon.A2.vsubws(i64, i64) #021declare i32 @llvm.hexagon.A4.modwrapu(i32, i32) #022 23define void @f0(i32 %a0, ptr %a1) #1 {24b0:25 br label %b126 27b1: ; preds = %b5, %b028 %v0 = phi i32 [ 0, %b0 ], [ %v26, %b5 ]29 %v1 = phi i32 [ 0, %b0 ], [ %v25, %b5 ]30 %v2 = load i32, ptr @g1, align 431 %v3 = load i32, ptr @g2, align 832 %v4 = and i32 %v3, %v233 br label %b234 35b2: ; preds = %b4, %b136 %v5 = phi i64 [ %v21, %b4 ], [ 0, %b1 ]37 %v6 = phi i64 [ %v22, %b4 ], [ 0, %b1 ]38 %v7 = phi i32 [ %v9, %b4 ], [ %v4, %b1 ]39 %v8 = tail call i32 @llvm.hexagon.S2.cl0(i32 %v7)40 %v9 = tail call i32 @llvm.hexagon.S2.setbit.r(i32 %v7, i32 %v8)41 %v10 = getelementptr [10 x %s.0], ptr inttoptr (i32 -121502345 to ptr), i32 0, i32 %v142 %v11 = getelementptr %s.0, ptr %v10, i32 0, i32 12, i32 %v843 %v12 = load i32, ptr %v11, align 444 %v13 = tail call i64 @llvm.hexagon.M2.vmpy2s.s0(i32 %v12, i32 %v12)45 %v14 = getelementptr %s.0, ptr %v10, i32 0, i32 13, i32 %v846 %v15 = load i32, ptr %v14, align 447 %v16 = tail call i64 @llvm.hexagon.M2.vmac2s.s0(i64 %v13, i32 %v15, i32 %v15)48 %v17 = load i8, ptr @g3, align 149 %v18 = and i8 %v17, 150 %v19 = icmp eq i8 %v18, 051 br i1 %v19, label %b3, label %b4, !prof !052 53b3: ; preds = %b254 %v20 = tail call i64 @llvm.hexagon.A2.vaddws(i64 %v5, i64 %v16)55 store i64 %v20, ptr %a1, align 856 br label %b457 58b4: ; preds = %b3, %b259 %v21 = phi i64 [ %v20, %b3 ], [ %v5, %b2 ]60 %v22 = tail call i64 @llvm.hexagon.A2.vsubws(i64 %v6, i64 %v16)61 %v23 = icmp eq i32 %v9, 062 br i1 %v23, label %b5, label %b2, !prof !163 64b5: ; preds = %b465 %v24 = add i32 %v1, 166 %v25 = tail call i32 @llvm.hexagon.A4.modwrapu(i32 %v24, i32 10) #067 %v26 = add i32 %v0, 168 %v27 = icmp eq i32 %v26, %a069 br i1 %v27, label %b6, label %b1, !prof !170 71b6: ; preds = %b572 store i64 %v16, ptr @g0, align 873 ret void74}75 76attributes #0 = { nounwind readnone }77attributes #1 = { nounwind }78 79!0 = !{!"branch_weights", i32 99, i32 1}80!1 = !{!"branch_weights", i32 10, i32 90}81