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1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2 3@v0 = global <16 x i32> zeroinitializer, align 644@v1 = global <16 x i32> zeroinitializer, align 645 6; CHECK-LABEL: danny:7; CHECK-NOT: vcombine8 9define void @danny() #0 {10 %t0 = load <16 x i32>, ptr @v0, align 6411 %t1 = load <16 x i32>, ptr @v1, align 6412 %t2 = call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %t0, <16 x i32> %t1)13 %t3 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %t2)14 %t4 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %t2)15 store <16 x i32> %t3, ptr @v0, align 6416 store <16 x i32> %t4, ptr @v1, align 6417 ret void18}19 20@w0 = global <32 x i32> zeroinitializer, align 12821@w1 = global <32 x i32> zeroinitializer, align 12822 23; CHECK-LABEL: sammy:24; CHECK-NOT: vcombine25 26define void @sammy() #1 {27 %t0 = load <32 x i32>, ptr @w0, align 12828 %t1 = load <32 x i32>, ptr @w1, align 12829 %t2 = call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> %t0, <32 x i32> %t1)30 %t3 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %t2)31 %t4 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %t2)32 store <32 x i32> %t3, ptr @w0, align 12833 store <32 x i32> %t4, ptr @w1, align 12834 ret void35}36 37declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #238declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #239declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #240 41declare <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32>, <32 x i32>) #342declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #343declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #344 45attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }46attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }47attributes #2 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }48attributes #3 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }49