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1# RUN: llc -march=hexagon -mcpu=hexagonv69 -mattr=+hvxv69,+hvx-length128b -run-pass hexagon-qfp-optimizer %s -o - | FileCheck %s2 3# CHECK: V6_vshuffvdd4# CHECK: V6_vadd_sf5# CHECK: V6_vadd_qf32_mix{{.*}}vsub_lo6# CHECK: V6_vadd_qf32_mix{{.*}}vsub_hi7 8---9name: qfp_subreg_fix10alignment: 1611tracksRegLiveness: true12 13body: |14 bb.0:15 %10:intregs = IMPLICIT_DEF16 %9:hvxvr = V6_vL32Ub_ai %10, 0 :: (load (s1024) from `ptr undef`, align 4)17 %11:intregs = A2_tfrsi 1536018 %12:hvxvr = V6_lvsplath %1119 %13:hvxwr = V6_vmpy_qf32_hf %9, %1220 %15:hvxvr = V6_vconv_sf_qf32 %13.vsub_lo21 %17:hvxvr = V6_vconv_sf_qf32 %13.vsub_hi22 %18:intregslow8 = A2_tfrsi -423 %19:hvxwr = V6_vshuffvdd %17, %15, %1824 %21:hvxvr = V6_vadd_sf %19.vsub_hi, %19.vsub_hi25 %22:hvxvr = V6_vconv_sf_qf32 %2126 %24:hvxvr = V6_vadd_sf %19.vsub_lo, %19.vsub_lo27 %25:hvxvr = V6_vconv_sf_qf32 %2428 %26:hvxvr = V6_vadd_sf %25, %19.vsub_lo29 %27:hvxvr = V6_vconv_sf_qf32 %2630 %28:hvxvr = V6_vadd_sf %22, %19.vsub_hi31 %29:hvxvr = V6_vconv_sf_qf32 %2832 33...34