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1; Tests if generated vadd instruction takes in qf322; type as first parameter instead of a sf type without3; any conversion instruction of type sf = qf324 5; RUN: llc -mtriple=hexagon -mattr=+hvx-length128b,+hvxv75,+v75 < %s -o - | FileCheck %s6 7; CHECK: [[V2:v[0-9]+]] = vxor([[V2]],[[V2]])8; CHECK: [[V0:v[0-9]+]].qf32 = vmpy([[V0]].sf,[[V2]].sf)9; CHECK: [[V1:v[0-9]+]].qf32 = vmpy([[V1]].sf,[[V2]].sf)10; CHECK: [[V4:v[0-9]+]].qf32 = vadd([[V0]].qf32,[[V2]].sf)11; CHECK: [[V5:v[0-9]+]].qf32 = vadd([[V1]].qf32,[[V2]].sf)12 13define void @_Z19compute_ripple_geluIDF16_EviPT_PKS0_(ptr %out_ptr, <64 x float> %conv14.ripple.vectorized) #0 {14entry:15 %mul16.ripple.vectorized = fmul <64 x float> %conv14.ripple.vectorized, zeroinitializer16 %conv17.ripple.vectorized = fptrunc <64 x float> %mul16.ripple.vectorized to <64 x half>17 store <64 x half> %conv17.ripple.vectorized, ptr %out_ptr, align 218 ret void19}20