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1; RUN: llc -mtriple=hexagon -O3 < %s | FileCheck %s2; REQUIRES: asserts3 4; Check that the code compiles successfully.5; CHECK: call f16 7target triple = "hexagon-unknown--elf"8 9%s.0 = type { i64, ptr, [4 x i32], [4 x i32], [4 x i32], i32, i8, i8, [6 x i8] }10 11; Function Attrs: nounwind12declare noalias ptr @f0() local_unnamed_addr #013 14; Function Attrs: nounwind15declare void @f1() local_unnamed_addr #016 17; Function Attrs: nounwind readnone18declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #119 20; Function Attrs: nounwind readnone21declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #122 23; Function Attrs: nounwind readnone24declare <32 x i32> @llvm.hexagon.V6.lvsplatw.128B(i32) #125 26; Function Attrs: nounwind readnone27declare <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32>, <32 x i32>) #128 29; Function Attrs: nounwind readnone30declare <32 x i32> @llvm.hexagon.V6.vlsrw.128B(<32 x i32>, i32) #131 32; Function Attrs: nounwind readnone33declare <32 x i32> @llvm.hexagon.V6.vshufeh.128B(<32 x i32>, <32 x i32>) #134 35; Function Attrs: nounwind readnone36declare <64 x i32> @llvm.hexagon.V6.vaddw.dv.128B(<64 x i32>, <64 x i32>) #137 38; Function Attrs: nounwind readnone39declare <32 x i32> @llvm.hexagon.V6.vasrh.128B(<32 x i32>, i32) #140 41; Function Attrs: nounwind readnone42declare <64 x i32> @llvm.hexagon.V6.vzh.128B(<32 x i32>) #143 44; Function Attrs: nounwind readnone45declare <32 x i32> @llvm.hexagon.V6.vaddh.128B(<32 x i32>, <32 x i32>) #146 47; Function Attrs: nounwind readnone48declare <64 x i32> @llvm.hexagon.V6.vmpyuh.128B(<32 x i32>, i32) #149 50; Function Attrs: nounwind readnone51declare <32 x i32> @llvm.hexagon.V6.vaslw.acc.128B(<32 x i32>, <32 x i32>, i32) #152 53; Function Attrs: nounwind readnone54declare <32 x i32> @llvm.hexagon.V6.valignb.128B(<32 x i32>, <32 x i32>, i32) #155 56; Function Attrs: noreturn nounwind57define void @f2(ptr noalias nocapture readonly %a01, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6) local_unnamed_addr #2 {58b0:59 %v0 = getelementptr inbounds %s.0, ptr %a01, i32 0, i32 160 %v2 = load ptr, ptr %v0, align 461 %v3 = tail call ptr @f0()62 %v4 = icmp sgt i32 %a1, 063 %v5 = select i1 %v4, i32 0, i32 %a164 %v6 = or i32 %v5, 165 %v7 = icmp sgt i32 %v6, 066 br i1 %v7, label %b1, label %b2, !prof !167 68b1: ; preds = %b069 br label %b470 71b2: ; preds = %b072 %v8 = ashr i32 %a6, 673 %v9 = mul i32 %v8, 6474 %v10 = add nsw i32 %v9, 25575 %v11 = icmp sgt i32 %a6, -19376 %v12 = ashr i32 %a5, 677 %v13 = ashr i32 %a4, 678 %v14 = ashr i32 %a2, 679 %v15 = icmp ult i32 %v10, 12880 %v16 = tail call ptr @f0()81 %v17 = icmp eq ptr %v16, null82 br i1 %v17, label %b6, label %b3, !prof !283 84b3: ; preds = %b285 %v18 = mul nsw i32 %v13, 1686 %v19 = mul nsw i32 %v13, 1987 %v20 = mul nsw i32 %v13, 1788 %v21 = mul nsw i32 %v13, 1889 br label %b790 91b4: ; preds = %b4, %b192 br label %b493 94b5: ; preds = %b895 br label %b696 97b6: ; preds = %b5, %b298 tail call void @f1() #399 unreachable100 101b7: ; preds = %b8, %b3102 %v22 = phi ptr [ %v16, %b3 ], [ %v28, %b8 ]103 %v23 = phi i32 [ 1, %b3 ], [ %v27, %b8 ]104 %v24 = sub i32 %v23, %a3105 %v25 = mul i32 %v24, %v12106 %v26 = sub i32 %v25, %v14107 br i1 %v11, label %b9, label %b8108 109b8: ; preds = %b13, %b7110 %v27 = add nuw nsw i32 %v23, 1111 %v28 = tail call ptr @f0()112 %v29 = icmp eq ptr %v28, null113 br i1 %v29, label %b5, label %b7, !prof !2114 115b9: ; preds = %b7116 %v30 = add i32 %v26, %v18117 %v31 = add i32 %v26, %v19118 %v32 = add i32 %v26, %v20119 %v33 = add i32 %v26, %v21120 %v34 = tail call <32 x i32> @llvm.hexagon.V6.lvsplatw.128B(i32 undef) #3121 %v35 = tail call <32 x i32> @llvm.hexagon.V6.lvsplatw.128B(i32 8) #3122 %v36 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> %v35, <32 x i32> %v35)123 br i1 %v15, label %b13, label %b10124 125b10: ; preds = %b9126 %v38 = tail call <64 x i32> @llvm.hexagon.V6.vzh.128B(<32 x i32> undef) #3127 %v39 = tail call <64 x i32> @llvm.hexagon.V6.vaddw.dv.128B(<64 x i32> undef, <64 x i32> %v38) #3128 %v40 = tail call <64 x i32> @llvm.hexagon.V6.vaddw.dv.128B(<64 x i32> %v39, <64 x i32> %v36) #3129 %v41 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %v40)130 %v42 = tail call <32 x i32> @llvm.hexagon.V6.vlsrw.128B(<32 x i32> %v41, i32 4) #3131 %v43 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> undef, <32 x i32> %v42)132 %v44 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %v43) #3133 %v45 = tail call <32 x i32> @llvm.hexagon.V6.vshufeh.128B(<32 x i32> undef, <32 x i32> %v44) #3134 br label %b11135 136b11: ; preds = %b11, %b10137 %v46 = phi <32 x i32> [ %v120, %b11 ], [ undef, %b10 ]138 %v47 = phi <32 x i32> [ %v115, %b11 ], [ undef, %b10 ]139 %v48 = phi <32 x i32> [ %v110, %b11 ], [ undef, %b10 ]140 %v49 = phi i32 [ %v124, %b11 ], [ 0, %b10 ]141 %v50 = phi i32 [ %v125, %b11 ], [ undef, %b10 ]142 %v51 = add i32 %v49, %v33143 %v52 = shl nsw i32 %v51, 6144 %v53 = getelementptr inbounds i16, ptr %v2, i32 %v52145 %v55 = load <32 x i32>, ptr %v53, align 128, !tbaa !3146 %v56 = add i32 %v49, %v32147 %v57 = shl nsw i32 %v56, 6148 %v58 = getelementptr inbounds i16, ptr %v2, i32 %v57149 %v60 = load <32 x i32>, ptr %v58, align 128, !tbaa !3150 %v61 = add i32 %v31, %v49151 %v62 = shl nsw i32 %v61, 6152 %v63 = getelementptr inbounds i16, ptr %v2, i32 %v62153 %v65 = load <32 x i32>, ptr %v63, align 128, !tbaa !3154 %v66 = add i32 %v49, %v30155 %v67 = shl nsw i32 %v66, 6156 %v68 = getelementptr inbounds i16, ptr %v2, i32 %v67157 %v70 = load <32 x i32>, ptr %v68, align 128, !tbaa !3158 %v71 = tail call <32 x i32> @llvm.hexagon.V6.valignb.128B(<32 x i32> %v55, <32 x i32> undef, i32 92)159 %v72 = tail call <32 x i32> @llvm.hexagon.V6.vasrh.128B(<32 x i32> %v71, i32 1) #3160 %v73 = tail call <32 x i32> @llvm.hexagon.V6.vaddh.128B(<32 x i32> %v72, <32 x i32> %v34) #3161 %v74 = tail call <64 x i32> @llvm.hexagon.V6.vmpyuh.128B(<32 x i32> %v73, i32 393222) #3162 %v75 = tail call <32 x i32> @llvm.hexagon.V6.valignb.128B(<32 x i32> %v60, <32 x i32> %v48, i32 92)163 %v76 = tail call <32 x i32> @llvm.hexagon.V6.vasrh.128B(<32 x i32> %v75, i32 1) #3164 %v77 = tail call <32 x i32> @llvm.hexagon.V6.vaddh.128B(<32 x i32> %v76, <32 x i32> %v34) #3165 %v78 = tail call <32 x i32> @llvm.hexagon.V6.valignb.128B(<32 x i32> %v65, <32 x i32> undef, i32 92)166 %v79 = tail call <32 x i32> @llvm.hexagon.V6.vasrh.128B(<32 x i32> %v78, i32 1) #3167 %v80 = tail call <32 x i32> @llvm.hexagon.V6.vaddh.128B(<32 x i32> %v79, <32 x i32> %v34) #3168 %v81 = tail call <32 x i32> @llvm.hexagon.V6.vaddh.128B(<32 x i32> %v77, <32 x i32> %v80) #3169 %v82 = tail call <64 x i32> @llvm.hexagon.V6.vzh.128B(<32 x i32> %v81) #3170 %v83 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v74)171 %v84 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v82)172 %v85 = tail call <32 x i32> @llvm.hexagon.V6.vaslw.acc.128B(<32 x i32> %v83, <32 x i32> %v84, i32 2) #3173 %v86 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> %v85, <32 x i32> undef)174 %v87 = tail call <32 x i32> @llvm.hexagon.V6.valignb.128B(<32 x i32> %v70, <32 x i32> %v47, i32 92)175 %v88 = tail call <32 x i32> @llvm.hexagon.V6.vasrh.128B(<32 x i32> %v87, i32 1) #3176 %v89 = tail call <32 x i32> @llvm.hexagon.V6.vaddh.128B(<32 x i32> %v88, <32 x i32> %v34) #3177 %v90 = tail call <32 x i32> @llvm.hexagon.V6.valignb.128B(<32 x i32> undef, <32 x i32> %v46, i32 92)178 %v91 = tail call <32 x i32> @llvm.hexagon.V6.vasrh.128B(<32 x i32> %v90, i32 1) #3179 %v92 = tail call <32 x i32> @llvm.hexagon.V6.vaddh.128B(<32 x i32> %v91, <32 x i32> %v34) #3180 %v93 = tail call <32 x i32> @llvm.hexagon.V6.vaddh.128B(<32 x i32> %v89, <32 x i32> %v92) #3181 %v94 = tail call <64 x i32> @llvm.hexagon.V6.vzh.128B(<32 x i32> %v93) #3182 %v95 = tail call <64 x i32> @llvm.hexagon.V6.vaddw.dv.128B(<64 x i32> %v86, <64 x i32> %v94) #3183 %v96 = tail call <64 x i32> @llvm.hexagon.V6.vaddw.dv.128B(<64 x i32> %v95, <64 x i32> %v36) #3184 %v97 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v96)185 %v98 = tail call <32 x i32> @llvm.hexagon.V6.vlsrw.128B(<32 x i32> %v97, i32 4) #3186 %v99 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> %v98, <32 x i32> undef)187 %v100 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %v99) #3188 %v101 = tail call <32 x i32> @llvm.hexagon.V6.vshufeh.128B(<32 x i32> undef, <32 x i32> %v100) #3189 %v102 = shl nsw i32 %v49, 6190 %v103 = getelementptr inbounds i16, ptr %v22, i32 %v102191 store <32 x i32> %v101, ptr %v103, align 128, !tbaa !6192 %v105 = or i32 %v49, 1193 %v106 = add i32 %v105, %v32194 %v107 = shl nsw i32 %v106, 6195 %v108 = getelementptr inbounds i16, ptr %v2, i32 %v107196 %v110 = load <32 x i32>, ptr %v108, align 128, !tbaa !3197 %v111 = add i32 %v105, %v30198 %v112 = shl nsw i32 %v111, 6199 %v113 = getelementptr inbounds i16, ptr %v2, i32 %v112200 %v115 = load <32 x i32>, ptr %v113, align 128, !tbaa !3201 %v116 = add i32 %v105, %v26202 %v117 = shl nsw i32 %v116, 6203 %v118 = getelementptr inbounds i16, ptr %v2, i32 %v117204 %v120 = load <32 x i32>, ptr %v118, align 128, !tbaa !3205 %v121 = shl nsw i32 %v105, 6206 %v122 = getelementptr inbounds i16, ptr %v22, i32 %v121207 store <32 x i32> %v45, ptr %v122, align 128, !tbaa !6208 %v124 = add nuw nsw i32 %v49, 2209 %v125 = add i32 %v50, -2210 %v126 = icmp eq i32 %v125, 0211 br i1 %v126, label %b12, label %b11212 213b12: ; preds = %b11214 br label %b13215 216b13: ; preds = %b12, %b9217 %v127 = phi i32 [ 0, %b9 ], [ %v124, %b12 ]218 %v128 = add i32 %v127, %v33219 %v129 = shl nsw i32 %v128, 6220 %v130 = getelementptr inbounds i16, ptr %v2, i32 %v129221 %v132 = load <32 x i32>, ptr %v130, align 128, !tbaa !3222 %v133 = add i32 %v127, %v30223 %v134 = shl nsw i32 %v133, 6224 %v135 = getelementptr inbounds i16, ptr %v2, i32 %v134225 %v137 = load <32 x i32>, ptr %v135, align 128, !tbaa !3226 %v138 = add i32 %v127, %v26227 %v139 = shl nsw i32 %v138, 6228 %v140 = getelementptr inbounds i16, ptr %v2, i32 %v139229 %v142 = load <32 x i32>, ptr %v140, align 128, !tbaa !3230 %v143 = tail call <32 x i32> @llvm.hexagon.V6.valignb.128B(<32 x i32> %v132, <32 x i32> undef, i32 92)231 %v144 = tail call <32 x i32> @llvm.hexagon.V6.vasrh.128B(<32 x i32> %v143, i32 1) #3232 %v145 = tail call <32 x i32> @llvm.hexagon.V6.vaddh.128B(<32 x i32> %v144, <32 x i32> %v34) #3233 %v146 = tail call <64 x i32> @llvm.hexagon.V6.vmpyuh.128B(<32 x i32> %v145, i32 393222) #3234 %v147 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v146)235 %v148 = tail call <32 x i32> @llvm.hexagon.V6.vaslw.acc.128B(<32 x i32> %v147, <32 x i32> undef, i32 2) #3236 %v149 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> %v148, <32 x i32> undef)237 %v150 = tail call <32 x i32> @llvm.hexagon.V6.valignb.128B(<32 x i32> %v137, <32 x i32> undef, i32 92)238 %v151 = tail call <32 x i32> @llvm.hexagon.V6.vasrh.128B(<32 x i32> %v150, i32 1) #3239 %v152 = tail call <32 x i32> @llvm.hexagon.V6.vaddh.128B(<32 x i32> %v151, <32 x i32> %v34) #3240 %v153 = tail call <32 x i32> @llvm.hexagon.V6.valignb.128B(<32 x i32> %v142, <32 x i32> undef, i32 92)241 %v154 = tail call <32 x i32> @llvm.hexagon.V6.vasrh.128B(<32 x i32> %v153, i32 1) #3242 %v155 = tail call <32 x i32> @llvm.hexagon.V6.vaddh.128B(<32 x i32> %v154, <32 x i32> %v34) #3243 %v156 = tail call <32 x i32> @llvm.hexagon.V6.vaddh.128B(<32 x i32> %v152, <32 x i32> %v155) #3244 %v157 = tail call <64 x i32> @llvm.hexagon.V6.vzh.128B(<32 x i32> %v156) #3245 %v158 = tail call <64 x i32> @llvm.hexagon.V6.vaddw.dv.128B(<64 x i32> %v149, <64 x i32> %v157) #3246 %v159 = tail call <64 x i32> @llvm.hexagon.V6.vaddw.dv.128B(<64 x i32> %v158, <64 x i32> %v36) #3247 %v160 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v159)248 %v161 = tail call <32 x i32> @llvm.hexagon.V6.vlsrw.128B(<32 x i32> %v160, i32 4) #3249 %v162 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> %v161, <32 x i32> undef)250 %v163 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v162) #3251 %v164 = tail call <32 x i32> @llvm.hexagon.V6.vshufeh.128B(<32 x i32> %v163, <32 x i32> undef) #3252 %v165 = getelementptr inbounds i16, ptr %v22, i32 undef253 store <32 x i32> %v164, ptr %v165, align 128, !tbaa !6254 br label %b8255}256 257attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }258attributes #1 = { nounwind readnone }259attributes #2 = { noreturn nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }260attributes #3 = { nounwind }261 262!llvm.module.flags = !{!0}263 264!0 = !{i32 2, !"halide_mattrs", !"+hvxv60,+hvx-length128b"}265!1 = !{!"branch_weights", i32 1073741824, i32 0}266!2 = !{!"branch_weights", i32 0, i32 1073741824}267!3 = !{!4, !4, i64 0}268!4 = !{!"input_yuv", !5}269!5 = !{!"Halide buffer"}270!6 = !{!7, !7, i64 0}271!7 = !{!"blurred_ds_y", !5}272