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1; RUN: llc -O3 -mtriple=hexagon < %s | FileCheck %s2; CHECK: v{{[0-9]+}} = vmem(r{{[0-9]+}}+#0)3 4target triple = "hexagon"5 6; Function Attrs: nounwind7define void @f0(ptr nocapture %a0) #0 {8b0:9 br i1 undef, label %b1, label %b510 11b1: ; preds = %b012 br label %b213 14b2: ; preds = %b4, %b115 %v1 = phi i32 [ 0, %b1 ], [ %v50, %b4 ]16 %v2 = phi ptr [ %a0, %b1 ], [ undef, %b4 ]17 br label %b318 19b3: ; preds = %b3, %b220 %v3 = phi i32 [ -4, %b2 ], [ %v40, %b3 ]21 %v4 = add i32 0, -6422 %v5 = getelementptr inbounds i8, ptr null, i32 %v423 %v7 = load <16 x i32>, ptr %v5, align 64, !tbaa !024 %v8 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> undef, <16 x i32> %v7, i32 4)25 %v9 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> %v8, <16 x i32> zeroinitializer)26 %v10 = tail call <64 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %v9, <16 x i32> undef)27 %v11 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<64 x i1> %v10, <16 x i32> undef, <16 x i32> undef)28 %v12 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<64 x i1> zeroinitializer, <16 x i32> %v11, <16 x i32> undef)29 %v13 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<64 x i1> undef, <16 x i32> %v12, <16 x i32> undef)30 %v14 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> undef, <16 x i32> undef, i32 1)31 %v15 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> %v14, <16 x i32> zeroinitializer)32 %v16 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> zeroinitializer, <16 x i32> zeroinitializer)33 %v17 = tail call <64 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> zeroinitializer, <16 x i32> undef)34 %v18 = tail call <64 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %v15, <16 x i32> undef)35 %v19 = tail call <64 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> zeroinitializer, <16 x i32> undef)36 %v20 = tail call <64 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %v16, <16 x i32> undef)37 %v21 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1> %v19, <16 x i32> undef, <16 x i32> zeroinitializer)38 %v22 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1> %v20, <16 x i32> undef, <16 x i32> zeroinitializer)39 %v23 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v22, <16 x i32> %v21)40 %v24 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> zeroinitializer, <32 x i32> %v23, i32 16843009)41 %v25 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<64 x i1> %v17, <16 x i32> %v13, <16 x i32> undef)42 %v26 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<64 x i1> %v18, <16 x i32> %v25, <16 x i32> undef)43 %v27 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<64 x i1> %v19, <16 x i32> %v26, <16 x i32> undef)44 %v28 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<64 x i1> %v20, <16 x i32> %v27, <16 x i32> undef)45 %v29 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> undef, <16 x i32> zeroinitializer)46 %v30 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> zeroinitializer, <16 x i32> zeroinitializer)47 %v31 = tail call <64 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> undef, <16 x i32> undef)48 %v32 = tail call <64 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %v29, <16 x i32> undef)49 %v33 = tail call <64 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %v30, <16 x i32> undef)50 %v34 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> %v24, <32 x i32> zeroinitializer, i32 16843009)51 %v35 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> %v34, <32 x i32> undef, i32 16843009)52 %v36 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<64 x i1> zeroinitializer, <16 x i32> %v28, <16 x i32> undef)53 %v37 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<64 x i1> %v31, <16 x i32> %v36, <16 x i32> undef)54 %v38 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<64 x i1> %v32, <16 x i32> %v37, <16 x i32> undef)55 %v39 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<64 x i1> %v33, <16 x i32> %v38, <16 x i32> undef)56 %v40 = add nsw i32 %v3, 357 %v41 = icmp eq i32 %v40, 558 br i1 %v41, label %b4, label %b359 60b4: ; preds = %b361 %v42 = phi <16 x i32> [ %v39, %b3 ]62 %v43 = phi <32 x i32> [ %v35, %b3 ]63 %v44 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v43)64 %v45 = tail call <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32> zeroinitializer, <16 x i32> %v44, i32 -2)65 %v46 = tail call <32 x i32> @llvm.hexagon.V6.vunpackub(<16 x i32> %v42)66 %v47 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v45)67 store <16 x i32> %v47, ptr %v2, align 64, !tbaa !068 %v48 = getelementptr inbounds <16 x i32>, ptr null, i32 169 %v49 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v46)70 store <16 x i32> %v49, ptr %v48, align 64, !tbaa !071 %v50 = add nsw i32 %v1, 172 %v51 = icmp slt i32 %v50, 073 br i1 %v51, label %b2, label %b574 75b5: ; preds = %b4, %b076 ret void77}78 79; Function Attrs: nounwind readnone80declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #181 82; Function Attrs: nounwind readnone83declare <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32>, <16 x i32>) #184 85; Function Attrs: nounwind readnone86declare <64 x i1> @llvm.hexagon.V6.vgtub(<16 x i32>, <16 x i32>) #187 88; Function Attrs: nounwind readnone89declare <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1>, <16 x i32>, <16 x i32>) #190 91; Function Attrs: nounwind readnone92declare <16 x i32> @llvm.hexagon.V6.vaddbnq(<64 x i1>, <16 x i32>, <16 x i32>) #193 94; Function Attrs: nounwind readnone95declare <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32>, <16 x i32>, i32) #196 97; Function Attrs: nounwind readnone98declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #199 100; Function Attrs: nounwind readnone101declare <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32>, <32 x i32>, i32) #1102 103; Function Attrs: nounwind readnone104declare <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32>, <16 x i32>, i32) #1105 106; Function Attrs: nounwind readnone107declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1108 109; Function Attrs: nounwind readnone110declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1111 112; Function Attrs: nounwind readnone113declare <32 x i32> @llvm.hexagon.V6.vunpackub(<16 x i32>) #1114 115attributes #0 = { null_pointer_is_valid nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }116attributes #1 = { nounwind readnone }117 118!0 = !{!1, !1, i64 0}119!1 = !{!"omnipotent char", !2, i64 0}120!2 = !{!"Simple C/C++ TBAA"}121