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1; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s2 3; Generate REG_SEQUENCE instead of combine4; CHECK-NOT: combine(#05 6; Function Attrs: nounwind7define void @f0(ptr nocapture readonly %a0, ptr nocapture readonly %a1, ptr nocapture %a2, ptr nocapture readonly %a3, i32 %a4) #0 {8b0:9 %v0 = lshr i32 %a4, 110 %v1 = icmp eq i32 %v0, 011 br i1 %v1, label %b3, label %b112 13b1: ; preds = %b014 br label %b215 16b2: ; preds = %b2, %b117 %v5 = phi i32 [ 0, %b1 ], [ %v71, %b2 ]18 %v6 = phi ptr [ %a0, %b1 ], [ %v9, %b2 ]19 %v7 = phi ptr [ %a1, %b1 ], [ %v11, %b2 ]20 %v8 = phi ptr [ %a2, %b1 ], [ %v70, %b2 ]21 %v9 = getelementptr inbounds i64, ptr %v6, i32 122 %v10 = load i64, ptr %v6, align 8, !tbaa !023 %v11 = getelementptr inbounds i64, ptr %v7, i32 124 %v12 = load i64, ptr %v7, align 8, !tbaa !025 %v13 = trunc i64 %v10 to i3226 %v14 = lshr i64 %v10, 3227 %v15 = tail call i64 @llvm.hexagon.S2.vzxthw(i32 %v13)28 %v16 = trunc i64 %v12 to i3229 %v17 = lshr i64 %v12, 3230 %v18 = tail call i64 @llvm.hexagon.S2.vzxthw(i32 %v16)31 %v19 = trunc i64 %v15 to i3232 %v20 = lshr i64 %v15, 3233 %v21 = getelementptr inbounds i16, ptr %a3, i32 %v1934 %v22 = load i16, ptr %v21, align 2, !tbaa !335 %v23 = trunc i64 %v20 to i3236 %v24 = getelementptr inbounds i16, ptr %a3, i32 %v2337 %v25 = load i16, ptr %v24, align 2, !tbaa !338 %v26 = trunc i64 %v18 to i3239 %v27 = lshr i64 %v18, 3240 %v28 = getelementptr inbounds i16, ptr %a3, i32 %v2641 %v29 = load i16, ptr %v28, align 2, !tbaa !342 %v30 = trunc i64 %v27 to i3243 %v31 = getelementptr inbounds i16, ptr %a3, i32 %v3044 %v32 = load i16, ptr %v31, align 2, !tbaa !345 %v33 = zext i16 %v32 to i6446 %v34 = shl nuw nsw i64 %v33, 3247 %v35 = zext i16 %v29 to i6448 %v36 = or i64 %v35, %v3449 %v37 = zext i16 %v25 to i6450 %v38 = shl nuw nsw i64 %v37, 3251 %v39 = zext i16 %v22 to i6452 %v40 = or i64 %v39, %v3853 %v41 = tail call i64 @llvm.hexagon.S2.vtrunewh(i64 %v36, i64 %v40)54 %v42 = getelementptr inbounds i64, ptr %v8, i32 155 store i64 %v41, ptr %v8, align 8, !tbaa !056 %v43 = trunc i64 %v14 to i3257 %v44 = tail call i64 @llvm.hexagon.S2.vzxthw(i32 %v43)58 %v45 = trunc i64 %v17 to i3259 %v46 = tail call i64 @llvm.hexagon.S2.vzxthw(i32 %v45)60 %v47 = trunc i64 %v44 to i3261 %v48 = lshr i64 %v44, 3262 %v49 = getelementptr inbounds i16, ptr %a3, i32 %v4763 %v50 = load i16, ptr %v49, align 2, !tbaa !364 %v51 = trunc i64 %v48 to i3265 %v52 = getelementptr inbounds i16, ptr %a3, i32 %v5166 %v53 = load i16, ptr %v52, align 2, !tbaa !367 %v54 = trunc i64 %v46 to i3268 %v55 = lshr i64 %v46, 3269 %v56 = getelementptr inbounds i16, ptr %a3, i32 %v5470 %v57 = load i16, ptr %v56, align 2, !tbaa !371 %v58 = trunc i64 %v55 to i3272 %v59 = getelementptr inbounds i16, ptr %a3, i32 %v5873 %v60 = load i16, ptr %v59, align 2, !tbaa !374 %v61 = zext i16 %v60 to i6475 %v62 = shl nuw nsw i64 %v61, 3276 %v63 = zext i16 %v57 to i6477 %v64 = or i64 %v63, %v6278 %v65 = zext i16 %v53 to i6479 %v66 = shl nuw nsw i64 %v65, 3280 %v67 = zext i16 %v50 to i6481 %v68 = or i64 %v67, %v6682 %v69 = tail call i64 @llvm.hexagon.S2.vtrunewh(i64 %v64, i64 %v68)83 %v70 = getelementptr inbounds i64, ptr %v8, i32 284 store i64 %v69, ptr %v42, align 8, !tbaa !085 %v71 = add nsw i32 %v5, 186 %v72 = icmp ult i32 %v71, %v087 br i1 %v72, label %b2, label %b388 89b3: ; preds = %b2, %b090 ret void91}92 93; Function Attrs: nounwind readnone94declare i64 @llvm.hexagon.S2.vzxthw(i32) #195 96; Function Attrs: nounwind readnone97declare i64 @llvm.hexagon.S2.vtrunewh(i64, i64) #198 99attributes #0 = { nounwind "target-cpu"="hexagonv60" }100attributes #1 = { nounwind readnone }101 102!0 = !{!1, !1, i64 0}103!1 = !{!"omnipotent char", !2, i64 0}104!2 = !{!"Simple C/C++ TBAA"}105!3 = !{!4, !4, i64 0}106!4 = !{!"short", !1, i64 0}107