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1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2 3; Check for a sane output. This testcase used to cause a crash.4; CHECK: vlut165 6target triple = "hexagon-unknown--elf"7 8declare void @halide_malloc() local_unnamed_addr #09 10declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #111declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #112declare <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32>, <32 x i32>) #113declare <32 x i32> @llvm.hexagon.V6.vmpyiewuh.128B(<32 x i32>, <32 x i32>) #114declare <64 x i32> @llvm.hexagon.V6.vaddw.dv.128B(<64 x i32>, <64 x i32>) #115declare <32 x i32> @llvm.hexagon.V6.vasrwhsat.128B(<32 x i32>, <32 x i32>, i32) #116declare <64 x i32> @llvm.hexagon.V6.vlutvwh.128B(<32 x i32>, <32 x i32>, i32) #117declare <64 x i32> @llvm.hexagon.V6.vlutvwh.oracc.128B(<64 x i32>, <32 x i32>, <32 x i32>, i32) #118 19define hidden void @fred(ptr %a0, i32 %a1, i1 %cond) #0 {20b0:21 %v1 = ashr i32 %a1, 722 %v2 = shl nsw i32 %v1, 723 switch i32 undef, label %b7 [24 i32 1, label %b325 i32 2, label %b526 i32 3, label %b627 ]28 29b3: ; preds = %b030 unreachable31 32b4: ; preds = %b733 switch i32 undef, label %b9 [34 i32 1, label %b835 i32 2, label %b1036 i32 3, label %b1137 ]38 39b5: ; preds = %b040 unreachable41 42b6: ; preds = %b043 unreachable44 45b7: ; preds = %b046 br label %b447 48b8: ; preds = %b449 br label %b1250 51b9: ; preds = %b452 br label %b1253 54b10: ; preds = %b455 br label %b1256 57b11: ; preds = %b458 br label %b1259 60b12: ; preds = %b11, %b10, %b9, %b861 br label %b1362 63b13: ; preds = %b14, %b1264 br label %b1465 66b14: ; preds = %b1367 br i1 undef, label %b15, label %b1368 69b15: ; preds = %b1470 br label %b1671 72b16: ; preds = %b1573 br i1 %cond, label %b17, label %b1874 75b17: ; preds = %b1676 unreachable77 78b18: ; preds = %b1679 tail call void @halide_malloc()80 br label %b1981 82b19: ; preds = %b1883 %v21 = icmp sgt i32 %a1, 084 br i1 %v21, label %b20, label %b2185 86b20: ; preds = %b1987 br label %b3288 89b21: ; preds = %b38, %b1990 %v22 = zext i32 %v2 to i6491 %v23 = lshr i64 %v22, 3192 %v24 = shl nuw nsw i64 %v23, 193 %v25 = or i64 %v24, 094 %v26 = icmp ult i64 %v23, 214748364895 %v27 = mul nuw nsw i64 %v25, 396 %v28 = add nuw nsw i64 %v27, 097 %v29 = and i64 %v28, 13314398617698 %v30 = icmp eq i64 %v29, 099 %v31 = and i1 %v26, %v30100 br label %b39101 102b32: ; preds = %b20103 %v33 = zext i32 %v2 to i64104 %v34 = mul nuw nsw i64 %v33, 12105 %v35 = icmp ult i64 %v34, 2147483648106 %v36 = and i1 %v35, undef107 br i1 %v36, label %b38, label %b37108 109b37: ; preds = %b32110 ret void111 112b38: ; preds = %b32113 tail call void @halide_malloc()114 br label %b21115 116b39: ; preds = %b42, %b21117 br label %b40118 119b40: ; preds = %b39120 br i1 %v31, label %b42, label %b41121 122b41: ; preds = %b40123 unreachable124 125b42: ; preds = %b40126 %v43 = tail call <64 x i32> @llvm.hexagon.V6.vlutvwh.128B(<32 x i32> undef, <32 x i32> undef, i32 0)127 %v44 = tail call <64 x i32> @llvm.hexagon.V6.vlutvwh.oracc.128B(<64 x i32> %v43, <32 x i32> undef, <32 x i32> undef, i32 1)128 %v45 = tail call <64 x i32> @llvm.hexagon.V6.vlutvwh.oracc.128B(<64 x i32> %v44, <32 x i32> undef, <32 x i32> undef, i32 2)129 %v46 = tail call <64 x i32> @llvm.hexagon.V6.vlutvwh.oracc.128B(<64 x i32> %v45, <32 x i32> undef, <32 x i32> undef, i32 3)130 %v47 = tail call <64 x i32> @llvm.hexagon.V6.vlutvwh.oracc.128B(<64 x i32> %v46, <32 x i32> undef, <32 x i32> undef, i32 4)131 %v48 = tail call <64 x i32> @llvm.hexagon.V6.vlutvwh.oracc.128B(<64 x i32> %v47, <32 x i32> undef, <32 x i32> undef, i32 5)132 %v49 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %v48)133 %v50 = tail call <32 x i32> @llvm.hexagon.V6.vmpyiewuh.128B(<32 x i32> undef, <32 x i32> %v49) #2134 %v51 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> undef, <32 x i32> %v50) #2135 %v52 = tail call <64 x i32> @llvm.hexagon.V6.vaddw.dv.128B(<64 x i32> %v51, <64 x i32> undef) #2136 %v53 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v52) #2137 %v54 = tail call <32 x i32> @llvm.hexagon.V6.vasrwhsat.128B(<32 x i32> %v53, <32 x i32> undef, i32 15) #2138 store <32 x i32> %v54, ptr %a0, align 128139 br label %b39140}141 142attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }143attributes #1 = { nounwind readnone }144attributes #2 = { nounwind }145