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1; RUN: llc -mtriple=hexagon < %s2; REQUIRES: asserts3 4; Test that register scvenging does not assert because of wrong5; bits being set for Kill and Def bit vectors in replaceSuperBySubRegs6 7%s.0 = type { i32, ptr, [0 x i32], [0 x i32], [1 x i32] }8%s.1 = type { %s.2, %s.4, %s.5 }9%s.2 = type { %s.3 }10%s.3 = type { i32 }11%s.4 = type { i32 }12%s.5 = type { [0 x i32], [0 x ptr] }13 14@g0 = common global i32 0, align 415@g1 = common global %s.0 zeroinitializer, align 416@g2 = common global i32 0, align 417@g3 = common global i32 0, align 418@g4 = common global ptr null, align 419@g5 = common global i32 0, align 420@g6 = common global i32 0, align 421 22; Function Attrs: nounwind23define i32 @f0(ptr nocapture readonly %a0) #0 {24b0:25 %v0 = alloca [0 x i32], align 426 %v1 = load i32, ptr @g0, align 4, !tbaa !027 %v3 = load i32, ptr %a0, align 4, !tbaa !028 %v4 = load ptr, ptr getelementptr inbounds (%s.0, ptr @g1, i32 0, i32 1), align 4, !tbaa !429 %v5 = load i32, ptr @g2, align 4, !tbaa !030 %v6 = sub i32 0, %v531 %v7 = getelementptr inbounds i32, ptr %v4, i32 %v632 %v8 = getelementptr inbounds %s.1, ptr %a0, i32 0, i32 1, i32 033 %v9 = load i32, ptr %v8, align 4, !tbaa !034 switch i32 %v9, label %b17 [35 i32 0, label %b136 i32 1, label %b237 ]38 39b1: ; preds = %b040 store i32 0, ptr @g3, align 4, !tbaa !041 br label %b242 43b2: ; preds = %b1, %b044 %v10 = icmp eq i32 %v1, 045 %v11 = icmp sgt i32 %v3, 046 %v13 = sdiv i32 %v3, 247 %v14 = add i32 %v13, -148 %v15 = getelementptr inbounds [0 x i32], ptr %v0, i32 0, i32 149 %v16 = getelementptr inbounds [0 x i32], ptr %v0, i32 0, i32 250 %v17 = getelementptr inbounds %s.1, ptr %a0, i32 0, i32 2, i32 1, i32 %v151 %v18 = getelementptr inbounds %s.1, ptr %a0, i32 0, i32 2, i32 1, i32 052 %v19 = sub i32 1, %v553 %v20 = getelementptr inbounds i32, ptr %v4, i32 %v1954 %v21 = sdiv i32 %v3, 455 %v22 = icmp slt i32 %v3, -356 %v23 = add i32 %v3, -157 %v24 = lshr i32 %v23, 258 %v25 = mul i32 %v24, 459 %v26 = add i32 %v25, 460 %v27 = add i32 %v13, -261 %v28 = icmp slt i32 %v26, 062 %v29 = add i32 %v21, 163 %v30 = select i1 %v22, i32 1, i32 %v2964 br label %b465 66b3: ; preds = %b1667 store i32 %v30, ptr @g3, align 4, !tbaa !068 br label %b469 70b4: ; preds = %b13, %b3, %b271 %v31 = phi i32 [ undef, %b2 ], [ %v87, %b3 ], [ %v87, %b13 ]72 %v32 = phi i32 [ undef, %b2 ], [ %v86, %b3 ], [ %v86, %b13 ]73 %v33 = phi i32 [ undef, %b2 ], [ %v35, %b3 ], [ %v35, %b13 ]74 %v34 = phi i32 [ undef, %b2 ], [ %v89, %b3 ], [ %v89, %b13 ]75 %v35 = phi i32 [ undef, %b2 ], [ %v94, %b3 ], [ %v65, %b13 ]76 br i1 %v10, label %b6, label %b577 78b5: ; preds = %b5, %b479 br label %b580 81b6: ; preds = %b482 br i1 %v11, label %b8, label %b783 84b7: ; preds = %b685 store i32 0, ptr @g3, align 4, !tbaa !086 br label %b1187 88b8: ; preds = %b689 store i32 %v26, ptr @g3, align 4, !tbaa !090 br i1 %v28, label %b9, label %b1191 92b9: ; preds = %b893 %v36 = load ptr, ptr @g4, align 4, !tbaa !794 br label %b1095 96b10: ; preds = %b10, %b997 %v37 = phi i32 [ %v26, %b9 ], [ %v45, %b10 ]98 %v38 = phi i32 [ %v34, %b9 ], [ %v44, %b10 ]99 %v39 = add nsw i32 %v37, %v33100 %v40 = shl i32 %v39, 1101 %v41 = getelementptr inbounds i32, ptr %v36, i32 %v40102 %v42 = load i32, ptr %v41, align 4, !tbaa !0103 %v43 = icmp slt i32 %v42, %v31104 %v44 = select i1 %v43, i32 0, i32 %v38105 %v45 = add nsw i32 %v37, 1106 store i32 %v45, ptr @g3, align 4, !tbaa !0107 %v46 = icmp slt i32 %v45, 0108 br i1 %v46, label %b10, label %b11109 110b11: ; preds = %b10, %b8, %b7111 %v47 = phi i32 [ %v26, %b8 ], [ 0, %b7 ], [ 0, %b10 ]112 %v48 = phi i32 [ %v34, %b8 ], [ %v34, %b7 ], [ %v44, %b10 ]113 %v49 = load i32, ptr @g5, align 4, !tbaa !0114 %v50 = icmp slt i32 %v13, %v49115 %v51 = icmp slt i32 %v47, %v14116 %v52 = and i1 %v50, %v51117 br i1 %v52, label %b12, label %b13118 119b12: ; preds = %b11120 %v53 = sub i32 %v27, %v47121 %v54 = lshr i32 %v53, 1122 %v55 = mul i32 %v54, 2123 %v56 = add i32 %v47, 2124 %v57 = add i32 %v56, %v55125 store i32 %v57, ptr @g3, align 4, !tbaa !0126 br label %b13127 128b13: ; preds = %b12, %b11129 %v58 = shl i32 %v35, 2130 %v59 = load ptr, ptr @g4, align 4, !tbaa !7131 %v60 = getelementptr inbounds i32, ptr %v59, i32 %v58132 %v61 = load i32, ptr %v60, align 4, !tbaa !0133 %v62 = load i32, ptr %v7, align 4, !tbaa !0134 %v63 = add nsw i32 %v62, %v61135 %v64 = add nsw i32 %v63, %v32136 store i32 %v64, ptr %v15, align 4, !tbaa !0137 %v65 = add i32 %v35, -1138 %v66 = getelementptr inbounds i32, ptr %v59, i32 %v65139 %v67 = load i32, ptr %v66, align 4, !tbaa !0140 %v68 = sub i32 %v49, %v5141 %v69 = getelementptr inbounds i32, ptr %v4, i32 %v68142 %v70 = load i32, ptr %v69, align 4, !tbaa !0143 %v71 = add nsw i32 %v70, %v67144 %v72 = load i32, ptr %v16, align 4, !tbaa !0145 %v73 = add nsw i32 %v71, %v72146 store i32 %v73, ptr %v16, align 4, !tbaa !0147 %v74 = load i32, ptr @g6, align 4, !tbaa !0148 %v75 = load ptr, ptr %v17, align 4, !tbaa !7149 %v76 = load i32, ptr getelementptr inbounds (%s.0, ptr @g1, i32 0, i32 4, i32 0), align 4, !tbaa !0150 %v77 = call i32 %v75(ptr getelementptr inbounds (%s.0, ptr @g1, i32 0, i32 4, i32 0), ptr null, ptr null, ptr null, ptr null, i32 %v76, ptr null) #0151 %v78 = load ptr, ptr %v18, align 4, !tbaa !7152 %v79 = inttoptr i32 %v74 to ptr153 %v80 = load i32, ptr getelementptr inbounds (%s.0, ptr @g1, i32 0, i32 4, i32 0), align 4, !tbaa !0154 %v81 = call i32 %v78(ptr getelementptr inbounds (%s.0, ptr @g1, i32 0, i32 4, i32 0), ptr null, ptr null, ptr null, ptr %v79, i32 %v80, ptr %v0) #0155 %v82 = load ptr, ptr @g4, align 4, !tbaa !7156 %v83 = getelementptr inbounds i32, ptr %v82, i32 %v58157 %v84 = load i32, ptr %v83, align 4, !tbaa !0158 %v85 = load i32, ptr %v20, align 4, !tbaa !0159 %v86 = add nsw i32 %v85, %v84160 store i32 %v86, ptr %v15, align 4, !tbaa !0161 %v87 = load i32, ptr %v0, align 4, !tbaa !0162 %v88 = icmp eq i32 %v87, 0163 %v89 = select i1 %v88, i32 %v48, i32 1164 store i32 %v89, ptr @g5, align 4, !tbaa !0165 store i32 0, ptr @g3, align 4, !tbaa !0166 br i1 %v22, label %b4, label %b14167 168b14: ; preds = %b16, %b13169 %v90 = phi i32 [ %v95, %b16 ], [ 0, %b13 ]170 %v91 = phi i32 [ %v94, %b16 ], [ %v65, %b13 ]171 br i1 %v88, label %b16, label %b15172 173b15: ; preds = %b14174 %v92 = mul i32 %v90, -4175 %v93 = add nsw i32 %v92, 1176 br label %b16177 178b16: ; preds = %b15, %b14179 %v94 = phi i32 [ %v93, %b15 ], [ %v91, %b14 ]180 %v95 = add nsw i32 %v90, 1181 %v96 = icmp slt i32 %v90, %v21182 br i1 %v96, label %b14, label %b3183 184b17: ; preds = %b0185 ret i32 undef186}187 188attributes #0 = { nounwind }189 190!0 = !{!1, !1, i64 0}191!1 = !{!"int", !2, i64 0}192!2 = !{!"omnipotent char", !3, i64 0}193!3 = !{!"Simple C/C++ TBAA"}194!4 = !{!5, !6, i64 4}195!5 = !{!"", !1, i64 0, !6, i64 4, !2, i64 8, !2, i64 8, !2, i64 8}196!6 = !{!"any pointer", !2, i64 0}197!7 = !{!6, !6, i64 0}198