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1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2 3; OR of two rotates of %a0(r0).4; CHECK-LABEL: f0:5; CHECK: r[[R00:[0-9]+]] = rol(r0,#7)6; CHECK: r[[R00]] |= rol(r0,#9)7define i32 @f0(i32 %a0) #0 {8b0:9 %v0 = shl i32 %a0, 710 %v1 = lshr i32 %a0, 2511 %v2 = or i32 %v0, %v112 %v3 = shl i32 %a0, 913 %v4 = lshr i32 %a0, 2314 %v5 = or i32 %v3, %v415 %v6 = or i32 %v2, %v516 ret i32 %v617}18 19; OR of two rotates of %a0(r0) with an extra input %a1(r1).20; CHECK-LABEL: f1:21; CHECK: r1 |= asl(r0,#7)22; CHECK: r1 |= rol(r0,#9)23define i32 @f1(i32 %a0, i32 %a1) #0 {24b0:25 %v0 = shl i32 %a0, 726 %v1 = lshr i32 %a0, 2527 %v2 = or i32 %v0, %a128 %v3 = shl i32 %a0, 929 %v4 = lshr i32 %a0, 2330 %v5 = or i32 %v3, %v431 %v6 = or i32 %v2, %v532 %v7 = or i32 %v6, %v133 ret i32 %v634}35 36; OR of two rotates of two different inputs: %a0(r0) and %a1(r1).37; CHECK-LABEL: f2:38; CHECK: r[[R20:[0-9]+]] = asl(r0,#11)39; CHECK: r[[R21:[0-9]+]] = lsr(r0,#21)40; CHECK: r[[R22:[0-9]+]] = lsr(r1,#13)41; CHECK: r[[R20]] |= asl(r1,#19)42; CHECK: r[[R20]] |= or(r[[R21]],r[[R22]])43define i32 @f2(i32 %a0, i32 %a1) #0 {44 %v0 = shl i32 %a0, 1145 %v1 = lshr i32 %a0, 2146 %v2 = shl i32 %a1, 1947 %v3 = lshr i32 %a1, 1348 %v4 = or i32 %v0, %v249 %v5 = or i32 %v1, %v350 %v6 = or i32 %v4, %v551 ret i32 %v652}53 54; ORs of multiple shifts of the same value with only one pair actually55; matching a rotate.56; CHECK-LABEL: f3:57; CHECK: r[[R30:[0-9]+]] = asl(r0,#3)58; CHECK: r[[R30]] |= asl(r0,#5)59; CHECK: r[[R30]] |= asl(r0,#7)60; CHECK: r[[R30]] |= asl(r0,#13)61; CHECK: r[[R30]] |= asl(r0,#19)62; CHECK: r[[R30]] |= lsr(r0,#2)63; CHECK: r[[R30]] |= lsr(r0,#15)64; CHECK: r[[R30]] |= lsr(r0,#23)65; CHECK: r[[R30]] |= lsr(r0,#25)66; CHECK: r[[R30]] |= lsr(r0,#30)67define i32 @f3(i32 %a0) #0 {68 %v0 = shl i32 %a0, 369 %v1 = shl i32 %a0, 570 %v2 = shl i32 %a0, 7 ; rotate71 %v3 = shl i32 %a0, 1372 %v4 = shl i32 %a0, 1973 %v5 = lshr i32 %a0, 274 %v6 = lshr i32 %a0, 1575 %v7 = lshr i32 %a0, 2376 %v8 = lshr i32 %a0, 25 ; rotate77 %v9 = lshr i32 %a0, 3078 %v10 = or i32 %v0, %v179 %v11 = or i32 %v10, %v280 %v12 = or i32 %v11, %v381 %v13 = or i32 %v12, %v482 %v14 = or i32 %v13, %v583 %v15 = or i32 %v14, %v684 %v16 = or i32 %v15, %v785 %v17 = or i32 %v16, %v886 %v18 = or i32 %v17, %v987 ret i32 %v1888}89 90attributes #0 = { readnone nounwind "target-cpu"="hexagonv60" "target-features"="-packets" }91