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1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2;3; Make sure that the A2_andp is not split.4;5; CHECK: loop0([[LOOP:.LBB[_0-9]+]],{{.*}})6; CHECK: [[LOOP]]:7; CHECK: and(r{{[0-9]+}}:{{[0-9]+}},r{{[0-9]+}}:{{[0-9]+}})8 9target triple = "hexagon"10 11define void @fred(i64 %a0, i64 %a1, i64 %a2, ptr nocapture %a3, i32 %a4) local_unnamed_addr #0 {12b5:13 %v6 = icmp sgt i32 %a4, 014 br i1 %v6, label %b7, label %b2015 16b7: ; preds = %b7, %b517 %v8 = phi ptr [ %v16, %b7 ], [ %a3, %b5 ]18 %v9 = phi i32 [ %v18, %b7 ], [ 0, %b5 ]19 %v10 = phi i64 [ %v17, %b7 ], [ %a0, %b5 ]20 %v11 = tail call i64 @llvm.hexagon.A2.andp(i64 %v10, i64 1085102592571150095)21 %v12 = tail call i32 @llvm.hexagon.A2.vcmpbgtu(i64 %a1, i64 %v11)22 %v13 = tail call i64 @llvm.hexagon.A2.vsubub(i64 %v11, i64 %a1)23 %v14 = and i32 %v12, 25524 %v15 = tail call i64 @llvm.hexagon.C2.vmux(i32 %v14, i64 %a2, i64 %v13)25 store i64 %v15, ptr %v8, align 826 %v16 = getelementptr i64, ptr %v8, i32 127 %v17 = load i64, ptr %v16, align 828 %v18 = add nuw nsw i32 %v9, 129 %v19 = icmp eq i32 %v18, %a430 br i1 %v19, label %b20, label %b731 32b20: ; preds = %b7, %b533 ret void34}35 36declare i64 @llvm.hexagon.A2.andp(i64, i64) #137declare i32 @llvm.hexagon.A2.vcmpbgtu(i64, i64) #138declare i64 @llvm.hexagon.A2.vsubub(i64, i64) #139declare i64 @llvm.hexagon.C2.vmux(i32, i64, i64) #140 41attributes #0 = { nounwind "target-cpu"="hexagonv60" }42attributes #1 = { nounwind readnone }43