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1; REQUIRES: to-be-fixed2; This requires further patches.3; RUN: llc -mtriple=hexagon < %s | FileCheck %s4;5; Split all andp/orp instructions (by boosting the profitability of their6; operands, which happen to be word masks).7; This should result in a loop with two packets, but we don't generate8; post-incremented loads, so we end up with 3 packets.9 10; CHECK-LABEL: fred11; CHECK: loop0([[LOOP:.LBB[0-9_]+]],12; CHECK: [[LOOP]]:13; CHECK: {14; CHECK: {15; Make sure that the 3rd packet only has an add in it.16; CHECK: {17; CHECK: r[[REG:[0-9]+]] = add(r[[REG]],#16)18; CHECK-NOT: {19; CHECK: }{{[ \t]*}}:endloop020 21target triple = "hexagon"22 23define i32 @fred(i32 %a0, ptr nocapture readonly %a1) local_unnamed_addr #0 {24b2:25 %v4 = getelementptr inbounds i32, ptr %a1, i32 126 %v5 = load i32, ptr %a1, align 427 %v6 = load i32, ptr %v4, align 428 %v7 = zext i32 %a0 to i6429 br label %b830 31b8: ; preds = %b8, %b232 %v9 = phi i32 [ %v6, %b2 ], [ %v49, %b8 ]33 %v10 = phi i32 [ %v5, %b2 ], [ %v48, %b8 ]34 %v11 = phi i32 [ 2, %b2 ], [ %v45, %b8 ]35 %v12 = phi i64 [ 0, %b2 ], [ %v46, %b8 ]36 %v13 = phi i64 [ 0, %b2 ], [ %v47, %b8 ]37 %v14 = phi i32 [ 0, %b2 ], [ %v33, %b8 ]38 %v15 = phi i32 [ 0, %b2 ], [ %v40, %b8 ]39 %v16 = zext i32 %v10 to i6440 %v17 = or i64 %v12, %v1641 %v18 = tail call i64 @llvm.hexagon.S4.vxsubaddhr(i64 %v17, i64 %v7)42 %v19 = zext i32 %v9 to i6443 %v20 = or i64 %v13, %v1944 %v21 = tail call i64 @llvm.hexagon.S4.vxsubaddhr(i64 %v20, i64 %v7)45 %v22 = getelementptr inbounds i32, ptr %a1, i32 %v1146 %v23 = load i32, ptr %v22, align 447 %v24 = or i32 %v11, 148 %v25 = getelementptr inbounds i32, ptr %a1, i32 %v2449 %v26 = load i32, ptr %v25, align 450 %v27 = zext i32 %v14 to i6451 %v28 = shl nuw i64 %v27, 3252 %v29 = zext i32 %v23 to i6453 %v30 = or i64 %v28, %v2954 %v31 = tail call i64 @llvm.hexagon.S4.vxaddsubhr(i64 %v30, i64 %v7)55 %v32 = lshr i64 %v31, 3256 %v33 = trunc i64 %v32 to i3257 %v34 = zext i32 %v15 to i6458 %v35 = shl nuw i64 %v34, 3259 %v36 = zext i32 %v26 to i6460 %v37 = or i64 %v35, %v3661 %v38 = tail call i64 @llvm.hexagon.S4.vxaddsubhr(i64 %v37, i64 %v7)62 %v39 = lshr i64 %v38, 3263 %v40 = trunc i64 %v39 to i3264 %v41 = add nuw nsw i32 %v11, 265 %v42 = getelementptr inbounds i32, ptr %a1, i32 %v4166 %v43 = add nuw nsw i32 %v11, 367 %v44 = getelementptr inbounds i32, ptr %a1, i32 %v4368 %v45 = add nuw nsw i32 %v11, 469 %v46 = and i64 %v18, -429496729670 %v47 = and i64 %v21, -429496729671 %v48 = load i32, ptr %v42, align 472 %v49 = load i32, ptr %v44, align 473 %v50 = icmp ult i32 %v45, 3074 br i1 %v50, label %b8, label %b5175 76b51: ; preds = %b877 %v52 = zext i32 %v48 to i6478 %v53 = or i64 %v46, %v5279 %v54 = add i64 %v53, %v780 %v55 = lshr i64 %v54, 3281 %v56 = trunc i64 %v55 to i3282 %v57 = zext i32 %v49 to i6483 %v58 = or i64 %v47, %v5784 %v59 = add i64 %v58, %v785 %v60 = lshr i64 %v59, 3286 %v61 = trunc i64 %v60 to i3287 %v62 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v33, i32 %v56)88 %v63 = lshr i64 %v62, 3289 %v64 = trunc i64 %v63 to i3290 %v65 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v40, i32 %v61)91 %v66 = lshr i64 %v65, 3292 %v67 = trunc i64 %v66 to i3293 %v68 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v67, i32 %v64)94 %v69 = lshr i64 %v68, 3295 %v70 = trunc i64 %v69 to i3296 ret i32 %v7097}98 99declare i64 @llvm.hexagon.S4.vxsubaddhr(i64, i64) #1100declare i64 @llvm.hexagon.S4.vxaddsubhr(i64, i64) #1101declare i64 @llvm.hexagon.A2.combinew(i32, i32) #1102 103attributes #0 = { nounwind readonly "target-cpu"="hexagonv60" }104attributes #1 = { nounwind readnone }105