107 lines · plain
1; RUN: llc -mtriple=hexagon < %s2; REQUIRES: asserts3 4; Test that the splitVecPredRegs pass in the Hexagon Peephole pass does not5; move a vector predicate definition illegally, which ends up causing an assert6; later. The assert occurs because there is a use of a register that does not7; have a correct definition.8 9define void @f0() local_unnamed_addr #0 {10b0:11 br label %b112 13b1: ; preds = %b014 br i1 undef, label %b2, label %b315 16b2: ; preds = %b117 unreachable18 19b3: ; preds = %b120 br label %b421 22b4: ; preds = %b323 br label %b524 25b5: ; preds = %b426 br i1 undef, label %b13, label %b627 28b6: ; preds = %b529 br label %b730 31b7: ; preds = %b632 br label %b833 34b8: ; preds = %b735 %v0 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> undef, i32 -1)36 br i1 undef, label %b9, label %b1137 38b9: ; preds = %b839 br label %b1240 41b10: ; preds = %b1242 br label %b1143 44b11: ; preds = %b10, %b845 %v1 = phi <64 x i1> [ %v0, %b8 ], [ undef, %b10 ]46 %v2 = tail call <64 x i1> @llvm.hexagon.V6.pred.and(<64 x i1> %v1, <64 x i1> undef)47 %v3 = tail call <16 x i32> @llvm.hexagon.V6.vaddbq(<64 x i1> %v2, <16 x i32> undef, <16 x i32> undef)48 %v4 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> undef, <16 x i32> %v3, i32 undef)49 %v5 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v4, <16 x i32> undef, i32 undef)50 %v6 = tail call <16 x i32> @llvm.hexagon.V6.vand(<16 x i32> %v5, <16 x i32> undef)51 %v7 = tail call <16 x i32> @llvm.hexagon.V6.vor(<16 x i32> %v6, <16 x i32> undef)52 %v8 = tail call <16 x i32> @llvm.hexagon.V6.vsatwh(<16 x i32> %v7, <16 x i32> undef)53 %v9 = tail call <32 x i32> @llvm.hexagon.V6.vshufoeb(<16 x i32> undef, <16 x i32> %v8)54 %v10 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v9)55 %v11 = tail call <16 x i32> @llvm.hexagon.V6.vor(<16 x i32> %v10, <16 x i32> undef)56 %v12 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v11, i32 -1)57 %v13 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %v12, i32 undef)58 tail call void @llvm.hexagon.V6.vmaskedstoreq(<64 x i1> undef, ptr undef, <16 x i32> %v13)59 unreachable60 61b12: ; preds = %b12, %b962 %v14 = phi i32 [ %v15, %b12 ], [ 0, %b9 ]63 %v15 = add nuw nsw i32 %v14, 164 %v16 = icmp slt i32 %v15, undef65 br i1 %v16, label %b12, label %b1066 67b13: ; preds = %b568 ret void69}70 71; Function Attrs: nounwind readnone72declare <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32) #173 74; Function Attrs: nounwind readnone75declare <64 x i1> @llvm.hexagon.V6.pred.and(<64 x i1>, <64 x i1>) #176 77; Function Attrs: nounwind readnone78declare <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32>, <16 x i32>, i32) #179 80; Function Attrs: nounwind readnone81declare <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1>, i32) #182 83; Function Attrs: argmemonly nounwind84declare void @llvm.hexagon.V6.vmaskedstoreq(<64 x i1>, ptr, <16 x i32>) #285 86; Function Attrs: nounwind readnone87declare <16 x i32> @llvm.hexagon.V6.vaddbq(<64 x i1>, <16 x i32>, <16 x i32>) #188 89; Function Attrs: nounwind readnone90declare <16 x i32> @llvm.hexagon.V6.vor(<16 x i32>, <16 x i32>) #191 92; Function Attrs: nounwind readnone93declare <16 x i32> @llvm.hexagon.V6.vand(<16 x i32>, <16 x i32>) #194 95; Function Attrs: nounwind readnone96declare <16 x i32> @llvm.hexagon.V6.vsatwh(<16 x i32>, <16 x i32>) #197 98; Function Attrs: nounwind readnone99declare <32 x i32> @llvm.hexagon.V6.vshufoeb(<16 x i32>, <16 x i32>) #1100 101; Function Attrs: nounwind readnone102declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1103 104attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }105attributes #1 = { nounwind readnone }106attributes #2 = { argmemonly nounwind }107