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1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2 3target triple = "hexagon"4 5; CHECK-LABEL: test1:6; CHECK-DAG: memw(r29+#12) = ##8757704177; CHECK-DAG: memw(r29+#8) = #518; CHECK-DAG: memh(r29+#6) = #509; CHECK-DAG: memb(r29+#5) = #4910define void @test1() {11b0:12 %v1 = alloca [1 x i8], align 113 %v2 = alloca i16, align 214 %v3 = alloca i32, align 415 %v4 = alloca i32, align 416 call void @llvm.lifetime.start(i64 1, ptr %v1)17 store i8 49, ptr %v1, align 118 call void @llvm.lifetime.start(i64 2, ptr %v2)19 store i16 50, ptr %v2, align 220 call void @llvm.lifetime.start(i64 4, ptr %v3)21 store i32 51, ptr %v3, align 422 call void @llvm.lifetime.start(i64 4, ptr %v4)23 store i32 875770417, ptr %v4, align 424 call void @test4(ptr %v1, ptr %v2, ptr %v3, ptr %v4)25 call void @llvm.lifetime.end(i64 4, ptr %v4)26 call void @llvm.lifetime.end(i64 4, ptr %v3)27 call void @llvm.lifetime.end(i64 2, ptr %v2)28 call void @llvm.lifetime.end(i64 1, ptr %v1)29 ret void30}31 32; CHECK-LABEL: test2:33; CHECK-DAG: memw(r29+#8) = #5134; CHECK-DAG: memh(r29+#6) = r{{[0-9]+}}35; CHECK-DAG: memb(r29+#5) = r{{[0-9]+}}36define void @test2() {37b0:38 %v1 = alloca [1 x i8], align 139 %v2 = alloca i16, align 240 %v3 = alloca i32, align 441 %v4 = alloca i32, align 442 %v5 = alloca [100 x i8], align 843 %v6 = alloca [101 x i8], align 844 call void @llvm.lifetime.start(i64 1, ptr %v1)45 store i8 49, ptr %v1, align 146 call void @llvm.lifetime.start(i64 2, ptr %v2)47 store i16 50, ptr %v2, align 248 call void @llvm.lifetime.start(i64 4, ptr %v3)49 store i32 51, ptr %v3, align 450 call void @llvm.lifetime.start(i64 4, ptr %v4)51 store i32 875770417, ptr %v4, align 452 call void @llvm.lifetime.start(i64 100, ptr %v5)53 call void @llvm.memset.p0.i32(ptr align 8 %v5, i8 0, i32 100, i1 false)54 store i8 50, ptr %v5, align 855 call void @llvm.lifetime.start(i64 101, ptr %v6)56 call void @llvm.memset.p0.i32(ptr align 8 %v6, i8 0, i32 101, i1 false)57 store i8 49, ptr %v6, align 858 call void @test3(ptr %v1, ptr %v2, ptr %v3, ptr %v4, ptr %v5, ptr %v6)59 call void @llvm.lifetime.end(i64 101, ptr %v6)60 call void @llvm.lifetime.end(i64 100, ptr %v5)61 call void @llvm.lifetime.end(i64 4, ptr %v4)62 call void @llvm.lifetime.end(i64 4, ptr %v3)63 call void @llvm.lifetime.end(i64 2, ptr %v2)64 call void @llvm.lifetime.end(i64 1, ptr %v1)65 ret void66}67 68declare void @llvm.lifetime.start(i64, ptr nocapture) #069declare void @llvm.lifetime.end(i64, ptr nocapture) #070declare void @llvm.memset.p0.i32(ptr nocapture writeonly, i8, i32, i1) #071 72declare void @test3(ptr, ptr, ptr, ptr, ptr, ptr)73declare void @test4(ptr, ptr, ptr, ptr)74 75attributes #0 = { argmemonly nounwind "target-cpu"="hexagonv60" }76