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1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2 3; Test that the store widening optimization correctly transforms to a wider4; instruction with a sub register. Recently, the store widening occurs in the5; DAG combiner, so this test doesn't fail any more.6 7; CHECK: memh({{r[0-9]+}}+#{{[0-9]+}}) =8 9%s.0 = type { %s.1, %s.2, ptr, ptr, i32, i8, i8, i32, i8, i8, i32, i32, i8, i32, ptr, [2 x ptr], %s.13, ptr, ptr, %s.26, i32, i32, i32 }10%s.1 = type { i64, [8 x i8] }11%s.2 = type { ptr, i32, i8 }12%s.3 = type { %s.1, %s.26, %s.26, i32, i32, i32, ptr, ptr, ptr, ptr, i32, ptr }13%s.4 = type { %s.5, %s.12 }14%s.5 = type { i32, i32, i32, i32, i32, i32, i32, i32, %s.6 }15%s.6 = type { %s.7 }16%s.7 = type { i32, i32, %s.8, %s.9, i32, [4 x %s.10], %s.11 }17%s.8 = type { i32, i32, i32 }18%s.9 = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }19%s.10 = type { i32, i32 }20%s.11 = type { i32, i32, i32, i32, i32, i32, i32, i32 }21%s.12 = type { i32, i32, i32, i32, i32, i32, i32 }22%s.13 = type { i32, i32, i32, ptr, ptr, ptr, ptr, i32 }23%s.14 = type { ptr, i8, i32, ptr, i32, ptr }24%s.15 = type { %s.16, %s.17, %s.19, %s.20, %s.21, %s.24 }25%s.16 = type { i64, i64, i64, i32 }26%s.17 = type { i16, i16, i8, [4 x %s.18], i8, i8 }27%s.18 = type { i32, i32 }28%s.19 = type { ptr, i32, ptr }29%s.20 = type { i8, i8, i32, i32, i8, i32, i32, i32, i32, i32 }30%s.21 = type { i32, %s.22 }31%s.22 = type { %s.23 }32%s.23 = type { i32, i32, i32, i32, i32, i32, i32 }33%s.24 = type { %s.25 }34%s.25 = type { i32, i32, i32, i32, i32, i32, i32 }35%s.26 = type { %s.27 }36%s.27 = type { i16, i16, i32, i32, i32 }37 38; Function Attrs: nounwind39define void @f0(ptr %a0, i1 %a1) #0 {40b0:41 %v0 = load i64, ptr %a0, align 842 br i1 %a1, label %b1, label %b243 44b1: ; preds = %b045 %v1 = trunc i64 %v0 to i3246 %v2 = inttoptr i32 %v1 to ptr47 %v3 = getelementptr inbounds %s.0, ptr %v2, i32 0, i32 848 store i8 0, ptr %v3, align 849 %v4 = getelementptr inbounds %s.0, ptr %v2, i32 0, i32 950 store i8 1, ptr %v4, align 151 %v5 = getelementptr inbounds %s.0, ptr %v2, i32 0, i32 652 store i8 1, ptr %v5, align 153 ret void54 55b2: ; preds = %b056 ret void57}58 59attributes #0 = { nounwind }60