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1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2 3; Check if S4_subi_asl_ri is being generated correctly.4 5; CHECK-LABEL: yes_sub_asl6; FIXME: We no longer get subi_asl here. 7; XCHECK: [[REG1:(r[0-9]+)]] = sub(#0,asl([[REG1]],#1))8; CHECK: [[REG1:(r[0-9]+)]] = asl([[REG1]],#1)9; CHECK: = sub(#0,[[REG1]])10 11; CHECK-LABEL: no_sub_asl12; CHECK: [[REG2:(r[0-9]+)]] = asl(r{{[0-9]+}},#1)13; CHECK: r{{[0-9]+}} = sub([[REG2]],r{{[0-9]+}})14 15%struct.rtx_def = type { i16, i8 }16 17@this_insn_number = external global i32, align 418 19; Function Attrs: nounwind20define void @yes_sub_asl(ptr %reg, ptr nocapture readonly %setter) #0 {21entry:22 %0 = load i16, ptr %reg, align 423 switch i16 %0, label %return [24 i16 2, label %if.end25 i16 5, label %if.end26 ]27 28if.end:29 %1 = load i16, ptr %setter, align 430 %cmp8 = icmp eq i16 %1, 5631 %conv9 = zext i1 %cmp8 to i3232 %2 = load i32, ptr @this_insn_number, align 433 %3 = mul i32 %2, -234 %sub = add nsw i32 %conv9, %335 tail call void @reg_is_born(ptr nonnull %reg, i32 %sub) #236 br label %return37 38return:39 ret void40}41 42declare void @reg_is_born(ptr, i32) #143 44; Function Attrs: nounwind45define void @no_sub_asl(ptr %reg, ptr nocapture readonly %setter) #0 {46entry:47 %0 = load i16, ptr %reg, align 448 switch i16 %0, label %return [49 i16 2, label %if.end50 i16 5, label %if.end51 ]52 53if.end:54 %1 = load i32, ptr @this_insn_number, align 455 %mul = mul nsw i32 %1, 256 %2 = load i16, ptr %setter, align 457 %cmp8 = icmp eq i16 %2, 5658 %conv9 = zext i1 %cmp8 to i3259 %sub = sub nsw i32 %mul, %conv960 tail call void @reg_is_born(ptr nonnull %reg, i32 %sub) #261 br label %return62 63return:64 ret void65}66 67attributes #0 = { nounwind "target-cpu"="hexagonv5" }68attributes #1 = { "target-cpu"="hexagonv5" }69attributes #2 = { nounwind }70