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1; RUN: llc -mtriple=hexagon -enable-pipeliner -pipeliner-max-stages=1 < %s -pipeliner-experimental-cg=true | FileCheck %s2 3; Test that we update the offset correctly for loads that are4; moved past stores. In these cases, we change the dependences5; to make it easier to move the instructions, and we have to update6; the register/offsets correctly after the schedule is finalized.7 8@g0 = common global [400 x i32] zeroinitializer, align 89@g1 = common global [400 x i32] zeroinitializer, align 810 11; Function Attrs: nounwind12define void @f0() #0 {13b0:14 br label %b215 16b1: ; preds = %b217 ret void18 19; CHECK: loop0(.LBB0_[[LOOP:.]],20; CHECK: .LBB0_[[LOOP]]:21; CHECK: = memd([[REG1:(r[0-9]+)]]+#8)22; CHECK: memd([[REG1]]++#8) =23; CHECK: }{{[ \t]*}}:endloop24 25b2: ; preds = %b2, %b026 %v0 = phi ptr [ @g0, %b0 ], [ %v11, %b2 ]27 %v1 = phi ptr [ @g1, %b0 ], [ %v12, %b2 ]28 %v2 = phi i32 [ 0, %b0 ], [ %v9, %b2 ]29 %v4 = load <2 x i32>, ptr %v0, align 830 %v5 = mul <2 x i32> %v4, <i32 7, i32 7>31 %v7 = load <2 x i32>, ptr %v1, align 832 %v8 = add <2 x i32> %v7, %v533 store <2 x i32> %v8, ptr %v1, align 834 %v9 = add nsw i32 %v2, 235 %v10 = icmp slt i32 %v2, 39836 %v11 = getelementptr i32, ptr %v0, i32 237 %v12 = getelementptr i32, ptr %v1, i32 238 br i1 %v10, label %b2, label %b139}40 41attributes #0 = { nounwind "target-cpu"="hexagonv55" }42