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1; RUN: llc -mtriple=hexagon -hexagon-initial-cfg-cleanup=0 < %s -pipeliner-experimental-cg=true | FileCheck %s2 3; Test that we generate the correct offsets for loads in the prolog4; after removing dependences on a post-increment instructions of the5; base register.6 7; CHECK: memh([[REG0:(r[0-9]+)]]+#0)8; CHECK: memh([[REG0]]+#2)9; CHECK: loop010 11; Function Attrs: nounwind readnone12declare i32 @llvm.hexagon.A2.sath(i32) #113 14; Function Attrs: nounwind readnone15declare i32 @llvm.hexagon.S2.asr.r.r.sat(i32, i32) #116 17; Function Attrs: nounwind readnone18declare i32 @llvm.hexagon.A2.asrh(i32) #119 20; Function Attrs: nounwind readnone21declare i32 @llvm.hexagon.A2.addsat(i32, i32) #122 23; Function Attrs: nounwind readnone24declare i32 @llvm.hexagon.M2.mpy.sat.ll.s1(i32, i32) #125 26define void @f0(i32 %a0) #0 align 2 {27b0:28 br label %b129 30b1: ; preds = %b031 br label %b232 33b2: ; preds = %b2, %b134 %v0 = phi ptr [ undef, %b1 ], [ %v14, %b2 ]35 %v1 = phi i32 [ 0, %b1 ], [ %v12, %b2 ]36 %v2 = load i16, ptr %v0, align 237 %v3 = sext i16 %v2 to i3238 %v4 = call i32 @llvm.hexagon.M2.mpy.sat.ll.s1(i32 undef, i32 %v3)39 %v5 = call i32 @llvm.hexagon.S2.asr.r.r.sat(i32 %v4, i32 undef)40 %v6 = call i32 @llvm.hexagon.A2.addsat(i32 %v5, i32 32768)41 %v7 = call i32 @llvm.hexagon.A2.asrh(i32 %v6)42 %v8 = call i32 @llvm.hexagon.S2.asr.r.r.sat(i32 %v7, i32 undef)43 %v9 = call i32 @llvm.hexagon.A2.sath(i32 %v8)44 %v10 = trunc i32 %v9 to i1645 store i16 %v10, ptr null, align 246 %v11 = trunc i32 %v7 to i1647 store i16 %v11, ptr %v0, align 248 %v12 = add nsw i32 %v1, 149 %v13 = icmp slt i32 %v12, %a050 %v14 = getelementptr i16, ptr %v0, i32 151 br i1 %v13, label %b2, label %b352 53b3: ; preds = %b254 unreachable55 56b4: ; No predecessors!57 unreachable58}59 60attributes #0 = { nounwind "target-cpu"="hexagonv55" }61attributes #1 = { nounwind readnone }62