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1; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 -enable-pipeliner < %s -pipeliner-experimental-cg=true | FileCheck %s2; RUN: llc -mtriple=hexagon -mcpu=hexagonv62 -enable-pipeliner < %s -pipeliner-experimental-cg=true | FileCheck --check-prefix=CHECK-V62 %s3; RUN: llc -mtriple=hexagon -mcpu=hexagonv65 -enable-pipeliner < %s -pipeliner-experimental-cg=true | FileCheck --check-prefix=CHECK-V65 %s4 5;6; Make sure we pipeline the loop and that we generate the correct7; base+offset values for the loads.8 9; CHECK: loop0(.LBB0_[[LOOP:.]],10; CHECK: .LBB0_[[LOOP]]:11; CHECK: r{{[0-9]+}} = memw([[REG1:(r[0-9]+)]]+#{{[0,4]}})12; CHECK: r{{[0-9]+}} = memw([[REG1]]++#4)13; CHECK: }{{[ \t]*}}:endloop14; CHECK-V62-NOT: }{{[ \t]*}}:mem_noshuf15; CHECK-V65: }{{[ \t]*}}:mem_noshuf16 17; Function Attrs: nounwind18define i32 @f0(ptr %a0) #0 {19b0:20 br label %b121 22b1: ; preds = %b1, %b023 %v0 = phi i32 [ %v7, %b1 ], [ 0, %b0 ]24 %v1 = getelementptr inbounds ptr, ptr %a0, i32 %v025 %v2 = load ptr, ptr %v1, align 426 store i32 0, ptr %v2, align 427 %v4 = load ptr, ptr %v1, align 428 %v5 = getelementptr inbounds i8, ptr %v4, i32 829 store i32 0, ptr %v5, align 430 %v7 = add nsw i32 %v0, 131 %v8 = icmp eq i32 %v7, 232 br i1 %v8, label %b2, label %b133 34b2: ; preds = %b135 ret i32 %v736}37 38attributes #0 = { nounwind }39