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1; RUN: llc -mtriple=hexagon -enable-pipeliner -enable-pipeliner-opt-size \2; RUN: -verify-machineinstrs -hexagon-initial-cfg-cleanup=0 \3; RUN: -enable-aa-sched-mi=false -hexagon-expand-condsets=0 \4; RUN: < %s -pipeliner-experimental-cg=true | FileCheck %s5 6; Disable expand-condsets because it will assert on undefined registers.7 8; Test that we change the CFG correctly for pipelined loops where the trip9; count is a compile-time constant, and the trip count is the same as the10; number of prolog blocks (i.e., stages).11 12; CHECK: memb(r{{[0-9]+}}+#0) =13; CHECK: memb(r{{[0-9]+}}+#0) =14 15; Function Attrs: nounwind optsize16define void @f0(i1 %x, i32 %y, ptr %p1, ptr %p2, ptr %p3) #0 {17b0:18 br label %b119 20b1: ; preds = %b5, %b021 %v0 = load i16, ptr %p1, align 2, !tbaa !022 %v1 = sext i16 %v0 to i3223 %v2 = load i16, ptr %p2, align 2, !tbaa !024 %v3 = sext i16 %v2 to i3225 %v4 = and i32 %v1, 726 %v5 = and i32 %v3, 727 br label %b228 29b2: ; preds = %b4, %b130 br label %b331 32b3: ; preds = %b3, %b233 %v6 = phi i32 [ 0, %b2 ], [ %v22, %b3 ]34 %v7 = add i32 %v6, %y35 %v8 = icmp slt i32 %y, %v736 %v9 = add nsw i32 %v7, 137 %v10 = select i1 %x, i32 1, i32 %v938 %v11 = add i32 %v10, 039 %v12 = getelementptr inbounds i8, ptr null, i32 %v1140 %v13 = load i8, ptr %v12, align 1, !tbaa !441 %v14 = zext i8 %v13 to i3242 %v15 = mul i32 %v14, %v443 %v16 = add i32 %v15, 044 %v17 = mul i32 %v16, %v545 %v18 = add i32 %v17, 3246 %v19 = add i32 %v18, 047 %v20 = lshr i32 %v19, 648 %v21 = trunc i32 %v20 to i849 store i8 %v21, ptr %p3, align 1, !tbaa !450 %v22 = add i32 %v6, 151 %v23 = icmp eq i32 %v22, 252 br i1 %v23, label %b4, label %b353 54b4: ; preds = %b355 br i1 true, label %b5, label %b256 57b5: ; preds = %b458 br i1 false, label %b1, label %b659 60b6: ; preds = %b561 ret void62}63 64attributes #0 = { null_pointer_is_valid nounwind optsize "target-cpu"="hexagonv55" }65 66!0 = !{!1, !1, i64 0}67!1 = !{!"short", !2}68!2 = !{!"omnipotent char", !3}69!3 = !{!"Simple C/C++ TBAA"}70!4 = !{!2, !2, i64 0}71