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1; RUN: llc -mtriple=hexagon -rdf-opt=0 < %s -pipeliner-experimental-cg=true -hoist-const-loads=false | FileCheck %s2 3; Test that we fixup a pipelined loop correctly when the number of4; stages is greater than the compile-time loop trip count. In this5; test, there are two prolog stages, but the loop executes only once.6; In the bug, the final CFG contains two iterations of the loop.7 8; CHECK-NOT: loop09; CHECK: r{{[0-9]+}} = mpyi10; CHECK-NOT: r{{[0-9]+}} = mpyi11 12define i32 @f0(ptr %a0) {13b0:14 br label %b115 16b1: ; preds = %b1, %b017 %v0 = phi i32 [ 0, %b0 ], [ %v9, %b1 ]18 %v1 = phi i32 [ 0, %b0 ], [ %v8, %b1 ]19 %v2 = load i32, ptr %a0, align 420 %v3 = add nsw i32 %v1, 121 %v4 = srem i32 %v2, 322 %v5 = icmp ne i32 %v4, 023 %v6 = sub nsw i32 0, %v224 %v7 = select i1 %v5, i32 %v6, i32 %v225 %v8 = mul nsw i32 %v3, %v726 %v9 = add nsw i32 %v0, 127 %v10 = icmp eq i32 %v9, 128 br i1 %v10, label %b2, label %b129 30b2: ; preds = %b131 %v11 = phi i32 [ %v8, %b1 ]32 br label %b333 34b3: ; preds = %b3, %b235 ret i32 %v1136}37