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1; RUN: llc -mtriple=hexagon < %s -pipeliner-experimental-cg=true | FileCheck %s2 3; Test that the pipeliner correctly fixes up the pipelined CFG when the loop4; has a constant trip count, and the trip count is less than the number of5; prolog blocks. Prior to the bug, the pipeliner deleted one extra prolog and6; epilog stage. We check this by counting the number of sxth instructions.7 8; CHECK: r{{[0-9]+}} = sxth(r{{[0-9]+}})9; CHECK: r{{[0-9]+}} = sxth(r{{[0-9]+}})10; CHECK: r{{[0-9]+}} = sxth(r{{[0-9]+}})11; CHECK: r{{[0-9]+}} = sxth(r{{[0-9]+}})12 13; Function Attrs: nounwind readonly14define signext i16 @f0(ptr nocapture readonly %a0, ptr nocapture readnone %a1, ptr nocapture readonly %a2, ptr nocapture readonly %a3, i16 signext %a4, i16 signext %a5, i16 signext %a6) #0 {15b0:16 %v0 = icmp sgt i16 %a5, 017 br i1 %v0, label %b1, label %b718 19b1: ; preds = %b020 %v1 = load i16, ptr %a0, align 221 %v2 = sext i16 %v1 to i3222 %v3 = load i16, ptr %a3, align 223 %v4 = sext i16 %v3 to i3224 br label %b225 26b2: ; preds = %b6, %b127 %v5 = phi i32 [ 2147483647, %b1 ], [ %v44, %b6 ]28 %v6 = phi i16 [ 0, %b1 ], [ %v45, %b6 ]29 %v7 = phi i16 [ 0, %b1 ], [ %v43, %b6 ]30 %v8 = phi ptr [ %a2, %b1 ], [ %v38, %b6 ]31 %v9 = load i16, ptr %v8, align 232 %v10 = sext i16 %v9 to i3233 %v11 = tail call i32 @llvm.hexagon.A2.subh.l16.sat.ll(i32 %v2, i32 %v10)34 %v12 = shl i32 %v11, 1635 %v13 = ashr exact i32 %v12, 1636 %v14 = tail call i32 @llvm.hexagon.M2.mpy.sat.ll.s1(i32 %v13, i32 %v4)37 %v15 = tail call i32 @llvm.hexagon.M2.hmmpyl.s1(i32 %v14, i32 %v13)38 %v16 = tail call i32 @llvm.hexagon.S2.asr.r.r.sat(i32 %v15, i32 10)39 %v17 = getelementptr inbounds i16, ptr %v8, i32 140 br label %b341 42b3: ; preds = %b3, %b243 %v18 = phi ptr [ %v8, %b2 ], [ %v19, %b3 ]44 %v19 = phi ptr [ %v17, %b2 ], [ %v38, %b3 ]45 %v20 = phi i32 [ %v16, %b2 ], [ %v36, %b3 ]46 %v21 = phi i32 [ 1, %b2 ], [ %v37, %b3 ]47 %v22 = getelementptr inbounds i16, ptr %a0, i32 %v2148 %v23 = load i16, ptr %v22, align 249 %v24 = sext i16 %v23 to i3250 %v25 = load i16, ptr %v19, align 251 %v26 = sext i16 %v25 to i3252 %v27 = tail call i32 @llvm.hexagon.A2.subh.l16.sat.ll(i32 %v24, i32 %v26)53 %v28 = shl i32 %v27, 1654 %v29 = ashr exact i32 %v28, 1655 %v30 = getelementptr inbounds i16, ptr %a3, i32 %v2156 %v31 = load i16, ptr %v30, align 257 %v32 = sext i16 %v31 to i3258 %v33 = tail call i32 @llvm.hexagon.M2.mpy.sat.ll.s1(i32 %v29, i32 %v32)59 %v34 = tail call i32 @llvm.hexagon.M2.hmmpyl.s1(i32 %v33, i32 %v29)60 %v35 = tail call i32 @llvm.hexagon.S2.asr.r.r.sat(i32 %v34, i32 10)61 %v36 = tail call i32 @llvm.hexagon.A2.addsat(i32 %v20, i32 %v35)62 %v37 = add i32 %v21, 163 %v38 = getelementptr inbounds i16, ptr %v18, i32 264 %v39 = icmp eq i32 %v37, 365 br i1 %v39, label %b4, label %b366 67b4: ; preds = %b368 %v40 = tail call i32 @llvm.hexagon.A2.subsat(i32 %v36, i32 %v5)69 %v41 = icmp slt i32 %v40, 070 br i1 %v41, label %b5, label %b671 72b5: ; preds = %b473 %v42 = tail call i32 @llvm.hexagon.A2.addsat(i32 %v36, i32 0)74 br label %b675 76b6: ; preds = %b5, %b477 %v43 = phi i16 [ %v6, %b5 ], [ %v7, %b4 ]78 %v44 = phi i32 [ %v42, %b5 ], [ %v5, %b4 ]79 %v45 = add i16 %v6, 180 %v46 = icmp eq i16 %v45, %a581 br i1 %v46, label %b7, label %b282 83b7: ; preds = %b6, %b084 %v47 = phi i16 [ 0, %b0 ], [ %v43, %b6 ]85 ret i16 %v4786}87 88; Function Attrs: nounwind readnone89declare i32 @llvm.hexagon.A2.subh.l16.sat.ll(i32, i32) #190 91; Function Attrs: nounwind readnone92declare i32 @llvm.hexagon.M2.mpy.sat.ll.s1(i32, i32) #193 94; Function Attrs: nounwind readnone95declare i32 @llvm.hexagon.M2.hmmpyl.s1(i32, i32) #196 97; Function Attrs: nounwind readnone98declare i32 @llvm.hexagon.S2.asr.r.r.sat(i32, i32) #199 100; Function Attrs: nounwind readnone101declare i32 @llvm.hexagon.A2.addsat(i32, i32) #1102 103; Function Attrs: nounwind readnone104declare i32 @llvm.hexagon.A2.subsat(i32, i32) #1105 106attributes #0 = { nounwind readonly "target-cpu"="hexagonv60" }107attributes #1 = { nounwind readnone }108