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1; RUN: llc -mtriple=hexagon -enable-pipeliner < %s2; REQUIRES: asserts3 4; Check that a dead REG_SEQUENCE doesn't ICE.5 6; Function Attrs: nounwind7define void @f0(ptr nocapture %a0, i32 %a1) #0 {8b0:9 %v0 = mul nsw i32 %a1, 410 %v1 = icmp sgt i32 %v0, 011 br i1 %v1, label %b1, label %b212 13b1: ; preds = %b1, %b014 %v2 = phi i32 [ %v11, %b1 ], [ 0, %b0 ]15 %v3 = load i32, ptr null, align 416 %v4 = zext i32 %v3 to i6417 %v6 = load i32, ptr %a0, align 418 %v7 = zext i32 %v6 to i6419 %v8 = shl nuw i64 %v7, 3220 %v9 = or i64 %v8, %v421 %v10 = tail call i64 @llvm.hexagon.M2.vdmacs.s0(i64 0, i64 %v9, i64 %v9)22 %v11 = add nsw i32 %v2, 423 %v12 = icmp slt i32 %v11, %v024 br i1 %v12, label %b1, label %b225 26b2: ; preds = %b1, %b027 %v13 = phi i64 [ 0, %b0 ], [ %v10, %b1 ]28 %v14 = tail call i64 @llvm.hexagon.S2.asr.r.vw(i64 %v13, i32 6)29 store i64 %v14, ptr null, align 830 unreachable31}32 33; Function Attrs: nounwind readnone34declare i64 @llvm.hexagon.M2.vdmacs.s0(i64, i64, i64) #135 36; Function Attrs: nounwind readnone37declare i64 @llvm.hexagon.S2.asr.r.vw(i64, i32) #138 39attributes #0 = { nounwind }40attributes #1 = { nounwind readnone }41