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1; RUN: llc -mtriple=hexagon -enable-pipeliner -hexagon-initial-cfg-cleanup=0 < %s -pipeliner-experimental-cg=true | FileCheck %s2 3; Test that the code that changes the dependences does not allow4; a load with a negative offset to be overlapped with the post5; increment store that generates the base register.6 7; CHECK: loop0(.LBB0_[[LOOP:.]],8; CHECK: .LBB0_[[LOOP]]:9; CHECK: = mem{{u?}}b([[REG:(r[0-9])+]]+#-1)10; CHECK-NOT: memb([[REG]]{{\+?}}#0) =11; CHECK: }12; CHECK: }{{[ \t]*}}:endloop013 14@g0 = external global [1000000 x i8], align 815 16; Function Attrs: nounwind17define void @f0(i32 %a0, ptr %a1, ptr %a2) #0 {18b0:19 br i1 undef, label %b1, label %b720 21b1: ; preds = %b022 br i1 undef, label %b2, label %b623 24b2: ; preds = %b5, %b125 br i1 undef, label %b3, label %b526 27b3: ; preds = %b3, %b228 %v0 = phi i32 [ %v17, %b3 ], [ 1, %b2 ]29 %v1 = phi i32 [ %v16, %b3 ], [ 0, %b2 ]30 %v2 = add nsw i32 %v0, -131 %v3 = getelementptr inbounds [1000 x i8], ptr %a1, i32 undef, i32 %v232 %v4 = load i8, ptr %v3, align 1, !tbaa !033 %v5 = zext i8 %v4 to i3234 %v6 = getelementptr inbounds [1000000 x i8], ptr @g0, i32 0, i32 %v135 %v7 = load i8, ptr %v6, align 1, !tbaa !036 %v8 = sext i8 %v7 to i3237 %v9 = getelementptr inbounds [1000 x i8], ptr %a2, i32 undef, i32 %v038 %v10 = load i8, ptr %v9, align 1, !tbaa !039 %v11 = sext i8 %v10 to i3240 %v12 = mul nsw i32 %v11, %v841 %v13 = add nsw i32 %v12, %v542 %v14 = trunc i32 %v13 to i843 %v15 = getelementptr inbounds [1000 x i8], ptr %a1, i32 undef, i32 %v044 store i8 %v14, ptr %v15, align 1, !tbaa !045 %v16 = add nsw i32 %v1, 146 %v17 = add nsw i32 %v0, 147 %v18 = icmp eq i32 %v17, %a048 br i1 %v18, label %b4, label %b349 50b4: ; preds = %b351 br label %b552 53b5: ; preds = %b4, %b254 br i1 undef, label %b6, label %b255 56b6: ; preds = %b5, %b157 unreachable58 59b7: ; preds = %b060 ret void61}62 63attributes #0 = { nounwind "target-cpu"="hexagonv55" }64 65!0 = !{!1, !1, i64 0}66!1 = !{!"omnipotent char", !2, i64 0}67!2 = !{!"Simple C/C++ TBAA"}68