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1; XFAIL: *2; Needs some fixed in the pipeliner.3; RUN: llc -mtriple=hexagon < %s -pipeliner-experimental-cg=true | FileCheck %s4 5; CHECK: endloop06; CHECK: vmem7; CHECK: vmem([[REG:r([0-9]+)]]+#1) =8; CHECK: vmem([[REG]]+#0) =9 10define void @f0(i32 %a0) local_unnamed_addr #0 {11b0:12 br label %b113 14b1: ; preds = %b1, %b015 %v0 = phi i32 [ %v33, %b1 ], [ %a0, %b0 ]16 %v1 = phi ptr [ %v32, %b1 ], [ undef, %b0 ]17 %v2 = phi ptr [ %v23, %b1 ], [ undef, %b0 ]18 %v3 = phi ptr [ %v10, %b1 ], [ undef, %b0 ]19 %v4 = phi ptr [ %v8, %b1 ], [ null, %b0 ]20 %v5 = phi <32 x i32> [ %v12, %b1 ], [ undef, %b0 ]21 %v6 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v5)22 %v7 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> %v6, <16 x i32> undef, i32 6)23 %v8 = getelementptr inbounds <16 x i32>, ptr %v4, i32 124 %v9 = load <16 x i32>, ptr %v4, align 6425 %v10 = getelementptr inbounds <16 x i32>, ptr %v3, i32 126 %v11 = load <16 x i32>, ptr %v3, align 6427 %v12 = tail call <32 x i32> @llvm.hexagon.V6.vsububh(<16 x i32> %v11, <16 x i32> %v9)28 %v13 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v12)29 %v14 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v13, <16 x i32> undef)30 %v15 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> %v14, <16 x i32> undef, i32 4)31 %v16 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v14, <16 x i32> %v15)32 %v17 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v14, <16 x i32> undef, i32 4)33 %v18 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v16, <16 x i32> undef, i32 2)34 %v19 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> undef, <16 x i32> %v17)35 %v20 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v18, <16 x i32> %v19)36 %v21 = getelementptr inbounds <16 x i32>, ptr %v2, i32 137 %v22 = load <16 x i32>, ptr %v2, align 6438 %v23 = getelementptr inbounds <16 x i32>, ptr %v2, i32 239 %v24 = load <16 x i32>, ptr %v21, align 6440 %v25 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v22, <16 x i32> %v7)41 %v26 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v24, <16 x i32> undef)42 %v27 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v25, <16 x i32> %v20)43 %v28 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v26, <16 x i32> %v20)44 store <16 x i32> %v27, ptr %v2, align 6445 store <16 x i32> %v28, ptr %v21, align 6446 %v29 = tail call <16 x i32> @llvm.hexagon.V6.vmpyhsrs(<16 x i32> %v27, i32 17760527)47 %v30 = tail call <16 x i32> @llvm.hexagon.V6.vmpyhsrs(<16 x i32> %v28, i32 17760527)48 %v31 = tail call <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32> %v30, <16 x i32> %v29)49 %v32 = getelementptr inbounds <16 x i32>, ptr %v1, i32 150 store <16 x i32> %v31, ptr %v1, align 6451 %v33 = add nsw i32 %v0, -6452 %v34 = icmp sgt i32 %v0, 19253 br i1 %v34, label %b1, label %b254 55b2: ; preds = %b156 unreachable57}58 59; Function Attrs: nounwind readnone60declare <32 x i32> @llvm.hexagon.V6.vsububh(<16 x i32>, <16 x i32>) #161 62; Function Attrs: nounwind readnone63declare <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32>, <16 x i32>) #164 65; Function Attrs: nounwind readnone66declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #167 68; Function Attrs: nounwind readnone69declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #170 71; Function Attrs: nounwind readnone72declare <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32>, <16 x i32>, i32) #173 74; Function Attrs: nounwind readnone75declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #176 77; Function Attrs: nounwind readnone78declare <16 x i32> @llvm.hexagon.V6.vmpyhsrs(<16 x i32>, i32) #179 80; Function Attrs: nounwind readnone81declare <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32>, <16 x i32>) #182 83attributes #0 = { nounwind "target-cpu"="hexagonv65" "target-features"="+hvxv65,+hvx-length64b" }84attributes #1 = { nounwind readnone }85