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1; RUN: llc -mtriple=hexagon -hexagon-initial-cfg-cleanup=0 -pipeliner-experimental-cg=true -disable-cgp-delete-phis -terminal-rule=0 < %s | FileCheck %s2 3; Test epilogue generation when reading loop-carried dependency from a previous4; stage. The first epilogue should read value from iteration N-1 of the kernel.5 6; CHECK: loop07; CHECK: r{{[0-9]+}} = add([[REG0:r([0-9]+)]],#8)8; CHECK: [[REG0]] = [[REG1:r([0-9]+)]]9; CHECK: endloop010; CHECK: = add([[REG1]],#8)11 12; Function Attrs: nounwind13define ptr @f0(ptr nocapture readonly %a0, i32 %a1, ptr noalias %p0, ptr noalias %p1, ptr noalias %p2) #0 {14b0:15 %v0 = alloca [129 x i32], align 816 %cond = freeze i1 poison17 br i1 %cond, label %b1, label %b318 19b1: ; preds = %b020 br label %b221 22b2: ; preds = %b2, %b123 %v1 = phi ptr [ %a0, %b1 ], [ %v2, %b2 ]24 %v2 = phi ptr [ %p0, %b1 ], [ %v15, %b2 ]25 %v3 = phi ptr [ %p1, %b1 ], [ %v4, %b2 ]26 %v4 = phi ptr [ %p1, %b1 ], [ %v14, %b2 ]27 %v5 = phi i32 [ 0, %b1 ], [ %v13, %b2 ]28 %v6 = phi ptr [ %p2, %b1 ], [ %v12, %b2 ]29 %v7 = load i16, ptr %v2, align 230 %v8 = sext i16 %v7 to i3231 %v9 = call i32 @llvm.hexagon.M2.mpy.ll.s0(i32 %v8, i32 %v8) #232 %v10 = load i16, ptr %v6, align 233 %v11 = call i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s0(i32 %v9, i32 undef, i32 undef) #234 store i32 %v11, ptr %v4, align 435 %v12 = getelementptr inbounds i16, ptr %v6, i32 -136 %v13 = add i32 %v5, 137 %v14 = getelementptr inbounds i32, ptr %v3, i32 238 %v15 = getelementptr inbounds i16, ptr %v1, i32 239 %v16 = icmp slt i32 %v13, %a140 br i1 %v16, label %b2, label %b341 42b3: ; preds = %b2, %b043 %out = phi ptr [ null, %b0 ], [ %v14, %b2 ]44 ret ptr %out45}46 47; Function Attrs: nounwind readnone48declare i32 @llvm.hexagon.M2.mpy.ll.s0(i32, i32) #149 50; Function Attrs: nounwind readnone51declare i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s0(i32, i32, i32) #152 53attributes #0 = { nounwind "target-cpu"="hexagonv60" }54attributes #1 = { nounwind readnone }55attributes #2 = { nounwind }56