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1; RUN: llc -mtriple=hexagon -hexagon-initial-cfg-cleanup=0 -pipeliner-experimental-cg=true < %s | FileCheck %s2 3; Test epilogue generation when reading loop-carried dependency in stage 1 from4; stage 0. Make sure the illegal phi the expender creates gets cleaned up5; correctly during peeling6 7; CHECK: loop08; CHECK: [[REG0:r([0-9]+)]] = add(r{{[0-9]+}},#8)9; CHECK: memw([[REG0]]+#0)10; CHECK: endloop011 12; Function Attrs: nounwind13define ptr @f0(ptr nocapture readonly %a0, i32 %a1, i32 %a2, i32 %a3, ptr %b, ptr %c) #0 {14b0:15  %cond = freeze i1 poison16  br i1 %cond, label %b1, label %b317 18b1:                                               ; preds = %b019  br label %b220 21b2:                                               ; preds = %b2, %b122  %v1 = phi ptr [ %a0, %b1 ], [ %v2, %b2 ]23  %v2 = phi ptr [ undef, %b1 ], [ %v15, %b2 ]24  %v3 = phi ptr [ %c, %b1 ], [ %v4, %b2 ]25  %v4 = phi ptr [ %c, %b1 ], [ %v14, %b2 ]26  %v5 = phi i32 [ 0, %b1 ], [ %v13, %b2 ]27  %v6 = phi ptr [ undef, %b1 ], [ %v12, %b2 ]28  %a = mul i32 %v5, %a229  %add = getelementptr inbounds i16, ptr %b, i32 %a30  %v7 = load i16, ptr %add, align 231  %v8 = sext i16 %v7 to i3232  %v9 = call i32 @llvm.hexagon.M2.mpy.ll.s0(i32 %v8, i32 %v8) #233  %v92 = call i32 @llvm.hexagon.M2.mpy.ll.s0(i32 %v9, i32 %v9) #234  %v93 = call i32 @llvm.hexagon.M2.mpy.ll.s0(i32 %v92, i32 %v92) #235  %v11 = call i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s0(i32 %v8, i32 undef, i32 undef) #236  store i32 %v11, ptr %v4, align 437  %v12 = getelementptr inbounds i16, ptr %v6, i32 -138  %v13 = add i32 %v5, 139  %v14 = getelementptr inbounds i32, ptr %v3, i32 240  store i32 %v93, ptr %v14, align 441  %v15 = getelementptr inbounds i16, ptr %v1, i32 242  %v16 = icmp slt i32 %v13, %a143  br i1 %v16, label %b2, label %b344 45b3:                                               ; preds = %b2, %b046  %out = phi ptr [ null, %b0 ], [ %v14, %b2 ]47  ret ptr %out48}49 50; Function Attrs: nounwind readnone51declare i32 @llvm.hexagon.M2.mpy.ll.s0(i32, i32) #152 53; Function Attrs: nounwind readnone54declare i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s0(i32, i32, i32) #155 56attributes #0 = { nounwind "target-cpu"="hexagonv60" }57attributes #1 = { nounwind readnone }58attributes #2 = { nounwind }59