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1; RUN: llc -mtriple=hexagon < %s -pipeliner-experimental-cg=true | FileCheck %s2 3; Test that we use the correct name in an epilog phi for a phi value4; that is defined for the last time in the kernel. Previously, we5; used the value from kernel loop definition, but we really need6; to use the value from the Phi in the kernel instead.7 8; In this test case, the second loop is pipelined, block b5.9 10; CHECK: loop111; CHECK: [[REG0:r([0-9]+)]] += mpyi12; CHECK: [[REG2:r([0-9]+)]] = add([[REG1:r([0-9]+)]],add([[REG0]],#813; CHECK: endloop114 15%s.0 = type { ptr, ptr, ptr, ptr, i8, i32, ptr, i32, i32, i32, i8, i8, i32, i32, double, i8, i8, i8, i8, i8, i8, i8, i8, i32, i8, i8, i8, i32, i32, i32, i32, i32, i32, ptr, i32, i32, i32, i32, i32, ptr, [4 x ptr], [4 x ptr], [4 x ptr], i32, ptr, i8, i8, [16 x i8], [16 x i8], [16 x i8], i32, i8, i8, i8, i8, i16, i16, i8, i8, i8, ptr, i32, i32, i32, i32, ptr, i32, [4 x ptr], i32, i32, i32, [10 x i32], i32, i32, i32, i32, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr }16%s.1 = type { ptr, ptr, ptr, ptr, ptr, i32, %s.3, i32, i32, ptr, i32, ptr, i32, i32 }17%s.2 = type { ptr, ptr, ptr, ptr, i8, i32 }18%s.3 = type { [8 x i32], [48 x i8] }19%s.4 = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32 }20%s.5 = type opaque21%s.6 = type opaque22%s.7 = type { ptr, i32, i32, i32, i32 }23%s.8 = type { ptr, i32, ptr, ptr, ptr, ptr, ptr }24%s.9 = type { [64 x i16], i8 }25%s.10 = type { [17 x i8], [256 x i8], i8 }26%s.11 = type { ptr, i8, i32, i32, ptr }27%s.12 = type { ptr, ptr, i8 }28%s.13 = type { ptr, ptr }29%s.14 = type { ptr, ptr, ptr, ptr, ptr }30%s.15 = type { ptr, ptr }31%s.16 = type { ptr, ptr, ptr, ptr, i8, i8 }32%s.17 = type { ptr, ptr, ptr, i8, i8, i32, i32 }33%s.18 = type { ptr, ptr, i8 }34%s.19 = type { ptr, [5 x ptr] }35%s.20 = type { ptr, ptr, i8 }36%s.21 = type { ptr, ptr }37%s.22 = type { ptr, ptr, ptr, ptr }38%s.23 = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8, i32, i32, i32, i32, i32, i32, ptr, ptr }39 40; Function Attrs: nounwind optsize41define hidden void @f0(ptr nocapture readonly %a0, ptr nocapture readonly %a1, ptr nocapture readonly %a2, ptr nocapture readonly %a3) #0 {42b0:43 %v0 = load ptr, ptr %a3, align 444 %v1 = getelementptr inbounds %s.0, ptr %a0, i32 0, i32 6245 %v2 = load i32, ptr %v1, align 446 %v3 = icmp sgt i32 %v2, 047 br i1 %v3, label %b1, label %b1048 49b1: ; preds = %b050 %v4 = getelementptr inbounds %s.23, ptr %a1, i32 0, i32 1051 br label %b252 53b2: ; preds = %b8, %b154 %v5 = phi i32 [ 0, %b1 ], [ %v98, %b8 ]55 %v6 = phi i32 [ 0, %b1 ], [ %v99, %b8 ]56 %v7 = getelementptr inbounds ptr, ptr %a2, i32 %v657 br label %b358 59b3: ; preds = %b7, %b260 %v8 = phi i32 [ 0, %b2 ], [ %v96, %b7 ]61 %v9 = phi i32 [ %v5, %b2 ], [ %v16, %b7 ]62 %v10 = load ptr, ptr %v7, align 463 %v11 = icmp eq i32 %v8, 064 %v12 = select i1 %v11, i32 -1, i32 165 %v13 = add i32 %v12, %v666 %v14 = getelementptr inbounds ptr, ptr %a2, i32 %v1367 %v15 = load ptr, ptr %v14, align 468 %v16 = add nsw i32 %v9, 169 %v17 = getelementptr inbounds ptr, ptr %v0, i32 %v970 %v18 = load ptr, ptr %v17, align 471 %v19 = getelementptr inbounds i8, ptr %v10, i32 172 %v20 = load i8, ptr %v10, align 173 %v21 = zext i8 %v20 to i3274 %v22 = mul nsw i32 %v21, 375 %v23 = getelementptr inbounds i8, ptr %v15, i32 176 %v24 = load i8, ptr %v15, align 177 %v25 = zext i8 %v24 to i3278 %v26 = add nsw i32 %v22, %v2579 %v27 = load i8, ptr %v19, align 180 %v28 = zext i8 %v27 to i3281 %v29 = mul nsw i32 %v28, 382 %v30 = load i8, ptr %v23, align 183 %v31 = zext i8 %v30 to i3284 %v32 = add nsw i32 %v29, %v3185 %v33 = mul nsw i32 %v26, 486 %v34 = add nsw i32 %v33, 887 %v35 = lshr i32 %v34, 488 %v36 = trunc i32 %v35 to i889 %v37 = getelementptr inbounds i8, ptr %v18, i32 190 store i8 %v36, ptr %v18, align 191 %v38 = mul nsw i32 %v26, 392 %v39 = add i32 %v38, 793 %v40 = add i32 %v39, %v3294 %v41 = lshr i32 %v40, 495 %v42 = trunc i32 %v41 to i896 store i8 %v42, ptr %v37, align 197 %v43 = load i32, ptr %v4, align 498 %v44 = add i32 %v43, -299 %v45 = getelementptr inbounds i8, ptr %v18, i32 2100 %v46 = icmp eq i32 %v44, 0101 br i1 %v46, label %b7, label %b4102 103b4: ; preds = %b3104 %v47 = getelementptr inbounds i8, ptr %v15, i32 2105 %v48 = getelementptr inbounds i8, ptr %v10, i32 2106 %v49 = mul i32 %v43, 2107 br label %b5108 109b5: ; preds = %b5, %b4110 %v50 = phi ptr [ %v45, %b4 ], [ %v76, %b5 ]111 %v51 = phi i32 [ %v44, %b4 ], [ %v75, %b5 ]112 %v52 = phi i32 [ %v26, %b4 ], [ %v53, %b5 ]113 %v53 = phi i32 [ %v32, %b4 ], [ %v64, %b5 ]114 %v54 = phi ptr [ %v18, %b4 ], [ %v50, %b5 ]115 %v55 = phi ptr [ %v47, %b4 ], [ %v61, %b5 ]116 %v56 = phi ptr [ %v48, %b4 ], [ %v57, %b5 ]117 %v57 = getelementptr inbounds i8, ptr %v56, i32 1118 %v58 = load i8, ptr %v56, align 1119 %v59 = zext i8 %v58 to i32120 %v60 = mul nsw i32 %v59, 3121 %v61 = getelementptr inbounds i8, ptr %v55, i32 1122 %v62 = load i8, ptr %v55, align 1123 %v63 = zext i8 %v62 to i32124 %v64 = add nsw i32 %v60, %v63125 %v65 = mul nsw i32 %v53, 3126 %v66 = add i32 %v52, 8127 %v67 = add i32 %v66, %v65128 %v68 = lshr i32 %v67, 4129 %v69 = trunc i32 %v68 to i8130 %v70 = getelementptr inbounds i8, ptr %v54, i32 3131 store i8 %v69, ptr %v50, align 1132 %v71 = add i32 %v65, 7133 %v72 = add i32 %v71, %v64134 %v73 = lshr i32 %v72, 4135 %v74 = trunc i32 %v73 to i8136 store i8 %v74, ptr %v70, align 1137 %v75 = add i32 %v51, -1138 %v76 = getelementptr inbounds i8, ptr %v50, i32 2139 %v77 = icmp eq i32 %v75, 0140 br i1 %v77, label %b6, label %b5141 142b6: ; preds = %b5143 %v78 = add i32 %v49, -2144 %v79 = getelementptr i8, ptr %v18, i32 %v78145 %v80 = add i32 %v49, -4146 %v81 = getelementptr i8, ptr %v18, i32 %v80147 br label %b7148 149b7: ; preds = %b6, %b3150 %v82 = phi ptr [ %v79, %b6 ], [ %v45, %b3 ]151 %v83 = phi i32 [ %v53, %b6 ], [ %v26, %b3 ]152 %v84 = phi i32 [ %v64, %b6 ], [ %v32, %b3 ]153 %v85 = phi ptr [ %v81, %b6 ], [ %v18, %b3 ]154 %v86 = mul nsw i32 %v84, 3155 %v87 = add i32 %v83, 8156 %v88 = add i32 %v87, %v86157 %v89 = lshr i32 %v88, 4158 %v90 = trunc i32 %v89 to i8159 %v91 = getelementptr inbounds i8, ptr %v85, i32 3160 store i8 %v90, ptr %v82, align 1161 %v92 = mul nsw i32 %v84, 4162 %v93 = add nsw i32 %v92, 7163 %v94 = lshr i32 %v93, 4164 %v95 = trunc i32 %v94 to i8165 store i8 %v95, ptr %v91, align 1166 %v96 = add nsw i32 %v8, 1167 %v97 = icmp eq i32 %v96, 2168 br i1 %v97, label %b8, label %b3169 170b8: ; preds = %b7171 %v98 = add i32 %v5, 2172 %v99 = add nsw i32 %v6, 1173 %v100 = load i32, ptr %v1, align 4174 %v101 = icmp slt i32 %v98, %v100175 br i1 %v101, label %b2, label %b9176 177b9: ; preds = %b8178 br label %b10179 180b10: ; preds = %b9, %b0181 ret void182}183 184attributes #0 = { nounwind optsize "target-cpu"="hexagonv60" }185