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1; RUN: llc -mtriple=hexagon -O2 -debug-only=pipeliner -hexagon-initial-cfg-cleanup=0 -disable-cgp-delete-phis < %s -o - 2>&1 > /dev/null | FileCheck %s2; REQUIRES: asserts3 4; Test that the phi in the first epilog block is getter the correct5; value from the kernel block. In this bug, the phi was using the value6; defined in the loop instead of the Phi valued defined in the kernel.7; We need to use the kernel's phi value (if the Phi in the kernel is the8; last definition).9 10; CHECK: New block11; CHECK: %[[REG:([0-9]+)]]:intregs = PHI %{{.*}}, %[[REG1:([0-9]+)]]12; CHECK: %[[REG1]]:intregs = nuw A2_addi13; CHECK: epilog:14; CHECK: %{{[0-9]+}}:intregs = PHI %{{.*}}, %[[REG]]15 16define void @f0(i32 %a0, i32 %a1, ptr noalias %p0, ptr noalias %p1) #0 {17b0:18 %v0 = icmp sgt i32 %a0, 6419 br i1 %v0, label %b1, label %b320 21b1: ; preds = %b022 br label %b223 24b2: ; preds = %b2, %b125 %v1 = phi i32 [ %a0, %b1 ], [ %v13, %b2 ]26 %v2 = phi ptr [ %p0, %b1 ], [ %v3, %b2 ]27 %v3 = getelementptr inbounds <16 x i32>, ptr %v2, i32 128 %v4 = load <16 x i32>, ptr %v2, align 6429 %v5 = load <16 x i32>, ptr undef, align 6430 %v6 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v5, <16 x i32> undef, i32 1)31 %v7 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> undef, <16 x i32> %v6)32 %v8 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> undef, <32 x i32> %v7, i32 undef)33 %v9 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32> %v8, <32 x i32> undef, i32 undef)34 %v10 = tail call <32 x i32> @llvm.hexagon.V6.vmpybus.acc(<32 x i32> %v9, <16 x i32> zeroinitializer, i32 undef)35 %v11 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v10)36 %v12 = tail call <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32> undef, <16 x i32> %v11, i32 %a1)37 store <16 x i32> %v12, ptr %p1, align 6438 %v13 = add nsw i32 %v1, -6439 %v14 = icmp sgt i32 %v13, 6440 br i1 %v14, label %b2, label %b341 42b3: ; preds = %b2, %b043 ret void44}45 46; Function Attrs: nounwind readnone47declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #048 49; Function Attrs: nounwind readnone50declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #051 52; Function Attrs: nounwind readnone53declare <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32>, <32 x i32>, i32) #054 55; Function Attrs: nounwind readnone56declare <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32>, <32 x i32>, i32) #057 58; Function Attrs: nounwind readnone59declare <32 x i32> @llvm.hexagon.V6.vmpybus.acc(<32 x i32>, <16 x i32>, i32) #060 61; Function Attrs: nounwind readnone62declare <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32>, <16 x i32>, i32) #063 64; Function Attrs: nounwind readnone65declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #066 67attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }68