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1; RUN: llc -mtriple=hexagon -mno-pairing -mno-compound -hexagon-initial-cfg-cleanup=0 < %s -pipeliner-experimental-cg=true | FileCheck %s2; XFAIL: *3 4; Test that we generate the correct phi names in the epilog when the pipeliner5; schedules a phi and it's loop definition in different stages, e.g., a phi is6; scheduled in stage 2, but the loop definition in scheduled in stage 0). The7; code in generateExistingPhis was generating the wrong name for the last8; epilog bock.9 10; CHECK: endloop011; CHECK: sub([[REG:r([0-9]+)]],r{{[0-9]+}}):sat12; CHECK-NOT: sub([[REG]],r{{[0-9]+}}):sat13 14define void @f0() {15b0:16 br label %b117 18b1: ; preds = %b1, %b019 br i1 undef, label %b2, label %b120 21b2: ; preds = %b122 br label %b323 24b3: ; preds = %b3, %b225 %v0 = phi i32 [ %v8, %b3 ], [ 7, %b2 ]26 %v1 = phi i32 [ %v6, %b3 ], [ undef, %b2 ]27 %v2 = phi i32 [ %v1, %b3 ], [ undef, %b2 ]28 %v3 = getelementptr inbounds [9 x i32], ptr undef, i32 0, i32 %v029 %v4 = add nsw i32 %v0, -230 %v5 = getelementptr inbounds [9 x i32], ptr undef, i32 0, i32 %v431 %v6 = load i32, ptr %v5, align 432 %v7 = tail call i32 @llvm.hexagon.A2.subsat(i32 %v2, i32 %v6)33 store i32 %v7, ptr %v3, align 434 %v8 = add i32 %v0, 135 %v9 = icmp sgt i32 %v8, 136 br i1 %v9, label %b3, label %b437 38b4: ; preds = %b339 unreachable40}41 42; Function Attrs: nounwind readnone43declare i32 @llvm.hexagon.A2.subsat(i32, i32) #044 45attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" }46