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1; RUN: llc -fp-contract=fast -O3 -mtriple=hexagon < %s2; REQUIRES: asserts3 4; Test that the pipeliner doesn't ICE due because the PHI generation5; code in the epilog does not attempt to reuse an existing PHI.6; Similar test case as swp-epilog-reuse.ll but with a couple of7; differences.8 9; Function Attrs: nounwind10define void @f0(ptr noalias %a0, ptr noalias %a1) #0 {11b0:12 %v0 = getelementptr inbounds float, ptr %a1, i32 213 br i1 undef, label %b1, label %b614 15b1: ; preds = %b5, %b016 %v1 = phi ptr [ undef, %b5 ], [ %v0, %b0 ]17 %v2 = phi ptr [ %v32, %b5 ], [ undef, %b0 ]18 %v3 = getelementptr inbounds float, ptr %a0, i32 undef19 %v4 = getelementptr inbounds float, ptr %v1, i32 120 br i1 undef, label %b2, label %b521 22b2: ; preds = %b123 %v5 = getelementptr float, ptr %v3, i32 124 br label %b325 26b3: ; preds = %b3, %b227 %v6 = phi ptr [ %v5, %b2 ], [ %v20, %b3 ]28 %v7 = phi float [ %v19, %b3 ], [ undef, %b2 ]29 %v8 = phi float [ %v7, %b3 ], [ undef, %b2 ]30 %v9 = phi ptr [ %v15, %b3 ], [ %v4, %b2 ]31 %v11 = fadd float undef, 0.000000e+0032 %v12 = fadd float undef, %v1133 %v13 = fadd float %v7, %v1234 %v14 = fmul float %v13, 3.906250e-0335 %v15 = getelementptr inbounds float, ptr %v9, i32 136 store float %v14, ptr %v9, align 4, !tbaa !037 %v16 = getelementptr i8, ptr %v6, i32 undef38 %v18 = load float, ptr %v16, align 4, !tbaa !039 %v19 = fadd float %v18, undef40 %v20 = getelementptr float, ptr %v6, i32 241 %v21 = icmp ult ptr %v15, %v242 br i1 %v21, label %b3, label %b443 44b4: ; preds = %b345 %v22 = getelementptr float, ptr %v4, i32 undef46 br label %b547 48b5: ; preds = %b4, %b149 %v23 = phi ptr [ %v4, %b1 ], [ %v22, %b4 ]50 %v24 = phi float [ undef, %b1 ], [ %v8, %b4 ]51 %v25 = fadd float %v24, undef52 %v26 = fadd float %v25, undef53 %v27 = fadd float undef, %v2654 %v28 = fadd float undef, %v2755 %v29 = fpext float %v28 to double56 %v30 = fmul double %v29, 0x3F7111112119E8FB57 %v31 = fptrunc double %v30 to float58 store float %v31, ptr %v23, align 4, !tbaa !059 %v32 = getelementptr inbounds float, ptr %v2, i32 undef60 br i1 undef, label %b1, label %b661 62b6: ; preds = %b5, %b063 ret void64}65 66attributes #0 = { nounwind "target-cpu"="hexagonv55" }67 68!0 = !{!1, !1, i64 0}69!1 = !{!"omnipotent char", !2, i64 0}70!2 = !{!"Simple C/C++ TBAA"}71