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1; RUN: llc -mtriple=hexagon -enable-pipeliner < %s2; REQUIRES: asserts3 4; Test that the pipeliner doesn't ICE due to incorrect PHI5; generation code that attemps to reuse an exsting PHI.6; Similar to the other swp-epillog-reuse test, but from a7; different test case.8 9; Function Attrs: nounwind readnone10declare i32 @llvm.hexagon.S2.asl.r.r.sat(i32, i32) #011 12; Function Attrs: nounwind13define void @f0() #1 {14b0:15 br label %b116 17b1: ; preds = %b1, %b018 br i1 undef, label %b2, label %b119 20b2: ; preds = %b2, %b121 br i1 undef, label %b3, label %b222 23b3: ; preds = %b3, %b224 %v0 = phi i16 [ %v10, %b3 ], [ undef, %b2 ]25 %v1 = phi i16 [ %v0, %b3 ], [ undef, %b2 ]26 %v2 = phi i32 [ %v26, %b3 ], [ undef, %b2 ]27 %v3 = phi ptr [ undef, %b3 ], [ undef, %b2 ]28 %v4 = phi ptr [ %v5, %b3 ], [ undef, %b2 ]29 %v5 = getelementptr inbounds i16, ptr %v4, i32 130 %v6 = sext i16 %v1 to i3231 %v7 = call i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32 0, i32 %v6, i32 undef)32 %v8 = getelementptr inbounds i16, ptr %v4, i32 233 %v9 = call i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32 %v7, i32 undef, i32 undef)34 %v10 = load i16, ptr %v8, align 2, !tbaa !035 %v11 = call i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32 %v9, i32 undef, i32 undef)36 %v12 = call i32 @llvm.hexagon.S2.asr.r.r.sat(i32 %v11, i32 undef)37 %v13 = getelementptr [166 x i32], ptr null, i32 0, i32 undef38 %v14 = load i32, ptr %v13, align 439 %v15 = call i64 @llvm.hexagon.M2.dpmpyss.s0(i32 %v14, i32 undef)40 %v16 = call i64 @llvm.hexagon.S2.asr.i.p(i64 %v15, i32 15)41 %v17 = call i32 @llvm.hexagon.A2.sat(i64 %v16)42 %v18 = call i32 @llvm.hexagon.A2.subsat(i32 %v12, i32 %v17)43 %v19 = getelementptr [166 x i32], ptr null, i32 0, i32 undef44 %v20 = load i32, ptr %v19, align 445 %v21 = call i64 @llvm.hexagon.M2.dpmpyss.s0(i32 %v20, i32 0)46 %v22 = call i64 @llvm.hexagon.S2.asr.i.p(i64 %v21, i32 15)47 %v23 = call i32 @llvm.hexagon.A2.sat(i64 %v22)48 %v24 = call i32 @llvm.hexagon.A2.subsat(i32 %v18, i32 %v23)49 %v25 = call i32 @llvm.hexagon.S2.asl.r.r.sat(i32 %v24, i32 undef)50 store i32 %v25, ptr %v3, align 4, !tbaa !451 %v26 = add i32 %v2, 152 %v27 = icmp eq i32 %v26, 16453 br i1 %v27, label %b4, label %b354 55b4: ; preds = %b356 call void @llvm.trap()57 unreachable58}59 60; Function Attrs: nounwind readnone61declare i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32, i32, i32) #062 63; Function Attrs: nounwind readnone64declare i32 @llvm.hexagon.S2.asr.r.r.sat(i32, i32) #065 66; Function Attrs: nounwind readnone67declare i32 @llvm.hexagon.A2.sat(i64) #068 69; Function Attrs: nounwind readnone70declare i64 @llvm.hexagon.S2.asr.i.p(i64, i32) #071 72; Function Attrs: nounwind readnone73declare i64 @llvm.hexagon.M2.dpmpyss.s0(i32, i32) #074 75; Function Attrs: nounwind readnone76declare i32 @llvm.hexagon.A2.subsat(i32, i32) #077 78; Function Attrs: noreturn nounwind79declare void @llvm.trap() #280 81attributes #0 = { nounwind readnone }82attributes #1 = { nounwind "target-cpu"="hexagonv55" }83attributes #2 = { noreturn nounwind }84 85!0 = !{!1, !1, i64 0}86!1 = !{!"short", !2, i64 0}87!2 = !{!"omnipotent char", !3, i64 0}88!3 = !{!"Simple C/C++ TBAA"}89!4 = !{!5, !5, i64 0}90!5 = !{!"long", !2, i64 0}91