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1; RUN: llc -mtriple=hexagon -enable-pipeliner -hexagon-expand-condsets=0 < %s2; REQUIRES: asserts3 4; Disable expand-condsets because it will assert on undefined registers.5 6; Another test that the pipeliner doesn't ICE when reusing a7; PHI in the epilog code.8 9@g0 = external global [18 x i16], align 810 11; Function Attrs: nounwind readnone12declare i32 @llvm.hexagon.S2.asl.r.r.sat(i32, i32) #013 14; Function Attrs: nounwind readnone15declare i32 @llvm.hexagon.A2.sxth(i32) #016 17; Function Attrs: nounwind18define void @f0() #1 {19b0:20 %v0 = alloca [166 x i32], align 821 br label %b122 23b1: ; preds = %b1, %b024 %v1 = icmp eq i16 undef, 025 br i1 %v1, label %b2, label %b126 27b2: ; preds = %b128 br i1 undef, label %b3, label %b429 30b3: ; preds = %b3, %b231 %v2 = add i32 0, 232 br i1 undef, label %b3, label %b433 34b4: ; preds = %b3, %b235 %v3 = phi ptr [ undef, %b2 ], [ undef, %b3 ]36 %v4 = phi i32 [ 0, %b2 ], [ %v2, %b3 ]37 %v5 = getelementptr [18 x i16], ptr @g0, i32 0, i32 undef38 br label %b539 40b5: ; preds = %b5, %b441 %v6 = phi i16 [ 0, %b4 ], [ %v17, %b5 ]42 %v7 = phi i16 [ undef, %b4 ], [ %v6, %b5 ]43 %v8 = phi i32 [ %v4, %b4 ], [ %v35, %b5 ]44 %v9 = phi ptr [ %v3, %b4 ], [ undef, %b5 ]45 %v10 = phi ptr [ undef, %b4 ], [ %v12, %b5 ]46 %v11 = add i32 %v8, 047 %v12 = getelementptr inbounds i16, ptr %v10, i32 148 %v13 = sext i16 %v7 to i3249 %v14 = call i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32 0, i32 %v13, i32 undef)50 %v15 = getelementptr inbounds i16, ptr %v10, i32 251 %v16 = call i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32 %v14, i32 undef, i32 undef)52 %v17 = load i16, ptr %v15, align 2, !tbaa !053 %v18 = sext i16 %v17 to i3254 %v19 = call i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32 %v16, i32 %v18, i32 undef)55 %v20 = call i32 @llvm.hexagon.S2.asr.r.r.sat(i32 %v19, i32 undef)56 %v21 = getelementptr [166 x i32], ptr %v0, i32 0, i32 %v1157 %v22 = load i32, ptr %v21, align 458 %v23 = call i64 @llvm.hexagon.M2.dpmpyss.s0(i32 %v22, i32 undef)59 %v24 = call i64 @llvm.hexagon.S2.asr.i.p(i64 %v23, i32 15)60 %v25 = call i32 @llvm.hexagon.A2.sat(i64 %v24)61 %v26 = call i32 @llvm.hexagon.A2.subsat(i32 %v20, i32 %v25)62 %v27 = load i16, ptr %v5, align 463 %v28 = sext i16 %v27 to i3264 %v29 = call i32 @llvm.hexagon.A2.sxth(i32 %v28)65 %v30 = call i64 @llvm.hexagon.M2.dpmpyss.s0(i32 undef, i32 %v29)66 %v31 = call i64 @llvm.hexagon.S2.asr.i.p(i64 %v30, i32 15)67 %v32 = call i32 @llvm.hexagon.A2.sat(i64 %v31)68 %v33 = call i32 @llvm.hexagon.A2.subsat(i32 %v26, i32 %v32)69 %v34 = call i32 @llvm.hexagon.S2.asl.r.r.sat(i32 %v33, i32 undef)70 store i32 %v34, ptr %v9, align 4, !tbaa !471 %v35 = add i32 %v8, 172 %v36 = icmp eq i32 %v35, 16473 br i1 %v36, label %b6, label %b574 75b6: ; preds = %b576 call void @llvm.trap()77 unreachable78}79 80; Function Attrs: nounwind readnone81declare i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32, i32, i32) #082 83; Function Attrs: nounwind readnone84declare i32 @llvm.hexagon.S2.asr.r.r.sat(i32, i32) #085 86; Function Attrs: nounwind readnone87declare i32 @llvm.hexagon.A2.sat(i64) #088 89; Function Attrs: nounwind readnone90declare i64 @llvm.hexagon.S2.asr.i.p(i64, i32) #091 92; Function Attrs: nounwind readnone93declare i64 @llvm.hexagon.M2.dpmpyss.s0(i32, i32) #094 95; Function Attrs: nounwind readnone96declare i32 @llvm.hexagon.A2.subsat(i32, i32) #097 98; Function Attrs: noreturn nounwind99declare void @llvm.trap() #2100 101attributes #0 = { nounwind readnone }102attributes #1 = { nounwind "target-cpu"="hexagonv55" }103attributes #2 = { noreturn nounwind }104 105!0 = !{!1, !1, i64 0}106!1 = !{!"short", !2, i64 0}107!2 = !{!"omnipotent char", !3, i64 0}108!3 = !{!"Simple C/C++ TBAA"}109!4 = !{!5, !5, i64 0}110!5 = !{!"long", !2, i64 0}111