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1; RUN: llc -mtriple=hexagon -enable-pipeliner < %s2; REQUIRES: asserts3 4; Make sure we fix up the Phis when we connect the last5; epilog block to the CFG.6 7define void @f0(ptr nocapture %a0) #0 {8b0:9  br i1 undef, label %b1, label %b210 11b1:                                               ; preds = %b012  br label %b313 14b2:                                               ; preds = %b015  unreachable16 17b3:                                               ; preds = %b3, %b118  br i1 undef, label %b4, label %b319 20b4:                                               ; preds = %b321  br i1 undef, label %b6, label %b522 23b5:                                               ; preds = %b424  store i16 4096, ptr %a0, align 225  br label %b1126 27b6:                                               ; preds = %b428  br i1 undef, label %b7, label %b829 30b7:                                               ; preds = %b7, %b631  br label %b732 33b8:                                               ; preds = %b8, %b634  br i1 undef, label %b9, label %b835 36b9:                                               ; preds = %b837  %v0 = icmp sgt i32 undef, 138  br i1 %v0, label %b10, label %b1139 40b10:                                              ; preds = %b10, %b941  %v1 = phi i32 [ %v8, %b10 ], [ 1, %b9 ]42  %v2 = getelementptr inbounds [11 x i32], ptr undef, i32 0, i32 %v143  %v3 = load i32, ptr undef, align 444  %v4 = add nsw i32 %v3, 045  %v5 = add nsw i32 %v4, 204846  %v6 = lshr i32 %v5, 1247  %v7 = trunc i32 %v6 to i1648  store i16 %v7, ptr undef, align 249  %v8 = add nsw i32 %v1, 150  %v9 = icmp eq i32 %v8, undef51  br i1 %v9, label %b11, label %b1052 53b11:                                              ; preds = %b10, %b9, %b554  %v10 = phi i1 [ false, %b9 ], [ false, %b5 ], [ %v0, %b10 ]55  br i1 undef, label %b16, label %b1256 57b12:                                              ; preds = %b1158  br i1 undef, label %b13, label %b1659 60b13:                                              ; preds = %b1261  br i1 %v10, label %b14, label %b1562 63b14:                                              ; preds = %b14, %b1364  br i1 undef, label %b15, label %b1465 66b15:                                              ; preds = %b14, %b1367  br label %b1668 69b16:                                              ; preds = %b15, %b12, %b1170  ret void71}72 73attributes #0 = { nounwind "target-cpu"="hexagonv55" }74