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1; RUN: llc -mtriple=hexagon -enable-pipeliner < %s2; REQUIRES: asserts3 4; Function Attrs: nounwind5define void @f0() #0 {6b0:7 br i1 undef, label %b1, label %b48 9b1: ; preds = %b010 br label %b211 12b2: ; preds = %b2, %b113 %v0 = phi i32 [ undef, %b1 ], [ %v13, %b2 ]14 %v1 = phi i32 [ 0, %b1 ], [ %v20, %b2 ]15 %v2 = zext i32 %v0 to i6416 %v3 = or i64 0, %v217 %v4 = tail call i64 @llvm.hexagon.S2.lsl.r.vh(i64 %v3, i32 4)18 %v5 = or i64 %v4, -922323129721890406419 %v6 = lshr i64 %v5, 3220 %v7 = trunc i64 %v6 to i3221 %v8 = tail call i64 @llvm.hexagon.S2.vzxthw(i32 %v7)22 %v9 = lshr i64 %v8, 3223 %v10 = trunc i64 %v9 to i3224 %v11 = tail call i32 @llvm.hexagon.S2.lsr.r.r(i32 %v10, i32 undef)25 %v12 = load i64, ptr undef, align 8, !tbaa !026 %v13 = trunc i64 %v12 to i3227 %v14 = lshr i64 %v12, 3228 %v15 = trunc i64 %v14 to i3229 %v16 = zext i32 %v11 to i6430 %v17 = shl nuw i64 %v16, 3231 %v18 = or i64 %v17, 032 %v19 = tail call i32 @llvm.hexagon.S2.vsatwuh(i64 %v18)33 %v20 = add nsw i32 %v1, 134 %v21 = icmp eq i32 %v20, undef35 br i1 %v21, label %b3, label %b236 37b3: ; preds = %b238 br label %b439 40b4: ; preds = %b3, %b041 %v22 = phi i32 [ %v19, %b3 ], [ undef, %b0 ]42 %v23 = phi i32 [ %v15, %b3 ], [ undef, %b0 ]43 %v24 = zext i32 %v22 to i6444 %v25 = shl nuw i64 %v24, 3245 %v26 = or i64 %v25, 046 store i64 %v26, ptr undef, align 8, !tbaa !047 ret void48}49 50; Function Attrs: nounwind readnone51declare i64 @llvm.hexagon.S2.lsl.r.vh(i64, i32) #152 53; Function Attrs: nounwind readnone54declare i64 @llvm.hexagon.S2.vzxthw(i32) #155 56; Function Attrs: nounwind readnone57declare i32 @llvm.hexagon.S2.lsr.r.r(i32, i32) #158 59; Function Attrs: nounwind readnone60declare i32 @llvm.hexagon.S2.vsatwuh(i64) #161 62attributes #0 = { nounwind "target-cpu"="hexagonv55" }63attributes #1 = { nounwind readnone }64 65!0 = !{!1, !1, i64 0}66!1 = !{!"long long", !2}67!2 = !{!"omnipotent char", !3}68!3 = !{!"Simple C/C++ TBAA"}69