75 lines · plain
1; RUN: llc -mtriple=hexagon -enable-pipeliner < %s2; REQUIRES: asserts3 4; This test caused an assert because there was a use of an instruction5; that was scheduled at stage 0, but no phi were added in the epilog.6 7%s.0 = type <{ ptr, ptr, i16, i8, i8, i8 }>8%s.1 = type { [4 x i16], [4 x i16], [4 x i16], [4 x i16], i32, i32, i32, i8, [10 x i32], [10 x [3 x i32]], [4 x i64], i8 }9%s.2 = type { [3 x i16], [4 x i8], i32, [3 x %s.3], [3 x %s.3], [3 x %s.3], [3 x %s.3], [3 x %s.3], [3 x %s.3], [6 x %s.3], [6 x %s.3], [6 x %s.3], i8, [3 x [3 x i16]], [3 x [3 x i16]], [3 x i16], [3 x i16], [6 x i16], [2 x i32], [10 x i32], [2 x i32], [2 x i32], [2 x [3 x i32]], [2 x i32], [2 x [3 x i64]], [2 x [3 x [3 x i32]]], [2 x [3 x i32]] }10%s.3 = type { i8, i8, i8, i8 }11 12@g0 = external constant %s.0, align 113 14define void @f0(i8 zeroext %a0, i32 %a1, i32 %a2, i8 zeroext %a3, ptr nocapture %a4, ptr %a5, i8 zeroext %a6) #0 {15b0:16 br i1 undef, label %b1, label %b717 18b1: ; preds = %b019 br i1 undef, label %b2, label %b320 21b2: ; preds = %b122 unreachable23 24b3: ; preds = %b125 %v0 = select i1 undef, i32 2, i32 426 %v1 = load i8, ptr undef, align 127 %v2 = zext i8 %v1 to i3228 %v3 = icmp uge i32 %v2, %v029 br label %b430 31b4: ; preds = %b4, %b332 br i1 undef, label %b4, label %b833 34b5: ; preds = %b1035 unreachable36 37b6: ; preds = %b1038 call void @f1(ptr @g0, i32 undef, i32 %v21, i32 undef, i32 undef)39 unreachable40 41b7: ; preds = %b042 ret void43 44b8: ; preds = %b8, %b445 %v4 = phi i32 [ %v11, %b8 ], [ undef, %b4 ]46 %v5 = phi i32 [ %v12, %b8 ], [ 0, %b4 ]47 %v6 = xor i1 false, %v348 %v7 = zext i1 %v6 to i3249 %v8 = shl nuw nsw i32 %v7, 150 %v9 = shl i32 %v4, 251 %v10 = or i32 0, %v952 %v11 = or i32 %v10, %v853 %v12 = add i32 %v5, 154 %v13 = icmp ult i32 %v12, %v055 br i1 %v13, label %b8, label %b956 57b9: ; preds = %b9, %b858 %v14 = phi i32 [ %v21, %b9 ], [ %v11, %b8 ]59 %v15 = icmp ne i32 undef, 160 %v16 = xor i1 %v15, %v361 %v17 = zext i1 %v16 to i3262 %v18 = shl nuw nsw i32 %v17, 163 %v19 = shl i32 %v14, 264 %v20 = or i32 0, %v1965 %v21 = or i32 %v20, %v1866 br i1 undef, label %b9, label %b1067 68b10: ; preds = %b969 br i1 undef, label %b6, label %b570}71 72declare void @f1(ptr, i32, i32, i32, i32)73 74attributes #0 = { nounwind "target-cpu"="hexagonv55" }75