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1; RUN: llc -mtriple=hexagon -enable-pipeliner-opt-size -hexagon-initial-cfg-cleanup=0 -terminal-rule=0 < %s -pipeliner-experimental-cg=true | FileCheck %s2 3; Test that we generate the correct names for the phis in the kernel for the4; incoming values. In this case, the loop contains a phi and has another phi5; as its loop definition, and the two phis are scheduled in different stages.6;7; vreg5 = phi(x, vreg4) is scheduled in stage 1, cycle 08; vreg4 = phi(y, z) is scheduled in stage 0, cycle 09 10; CHECK-DAG: :[[REG0:[0-9]+]]{{.*}} = {{.*}},#1711; CHECK-DAG: loop0(.LBB0_[[LOOP:.]],12; CHECK: .LBB0_[[LOOP]]:13; CHECK: r{{[0-9]+}} = sxth(r[[REG0]])14; CHECK: endloop015 16; Function Attrs: nounwind optsize17define void @f0() #0 {18b0:19 %v0 = getelementptr [8 x i16], ptr undef, i32 0, i32 720 br label %b221 22b1: ; preds = %b223 unreachable24 25b2: ; preds = %b2, %b026 %v2 = phi i32 [ 7, %b0 ], [ %v11, %b2 ]27 %v3 = phi i16 [ 17, %b0 ], [ %v7, %b2 ]28 %v4 = phi i16 [ 18, %b0 ], [ %v3, %b2 ]29 %v5 = sext i16 %v4 to i3230 %v6 = getelementptr i16, ptr null, i32 -231 %v7 = load i16, ptr %v6, align 232 %v8 = sext i16 %v7 to i3233 %v9 = tail call i32 @llvm.hexagon.A2.subsat(i32 %v5, i32 %v8)34 %v10 = trunc i32 %v9 to i1635 store i16 %v10, ptr null, align 236 %v11 = add nsw i32 %v2, -137 %v12 = icmp sgt i32 %v11, 138 br i1 %v12, label %b2, label %b139}40 41; Function Attrs: nounwind readnone42declare i32 @llvm.hexagon.A2.subsat(i32, i32) #143 44attributes #0 = { nounwind optsize "target-cpu"="hexagonv60" }45attributes #1 = { nounwind readnone }46