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1; RUN: llc -mtriple=hexagon -hexagon-initial-cfg-cleanup=0 < %s -pipeliner-experimental-cg=true | FileCheck %s2 3; Test that the pipeliner schedules a store before the load in which there is a4; loop carried dependence. Previously, the loop carried dependence wasn't added5; and the load from iteration n was scheduled prior to the store from iteration6; n-1.7 8; CHECK: loop0(.LBB0_[[LOOP:.]],9; CHECK: .LBB0_[[LOOP]]:10; CHECK: memh({{.*}}) =11; CHECK: = memuh({{.*}})12; CHECK: endloop013 14%s.0 = type { i16, i16 }15 16; Function Attrs: nounwind17define void @f0() local_unnamed_addr #0 {18b0:19 br label %b120 21b1: ; preds = %b1, %b022 %v0 = phi i32 [ 0, %b0 ], [ %v22, %b1 ]23 %v1 = load ptr, ptr undef, align 424 %v3 = load i16, ptr %v1, align 225 %v4 = add i16 0, %v326 %v5 = add i16 %v4, 027 %v6 = add i16 %v5, 028 %v7 = add i16 %v6, 029 %v8 = add i16 %v7, 030 %v9 = add i16 %v8, 031 %v10 = add i16 %v9, 032 %v11 = add i16 %v10, 033 %v12 = add i16 %v11, 034 %v13 = add i16 %v12, 035 %v14 = add i16 %v13, 036 %v15 = add i16 %v14, 037 %v16 = add i16 %v15, 038 %v17 = add i16 %v16, 039 %v18 = add i16 %v17, 040 %v19 = add i16 %v18, 041 %v20 = load ptr, ptr undef, align 442 store i16 %v19, ptr undef, align 243 %v21 = getelementptr inbounds %s.0, ptr %v20, i32 0, i32 144 store i16 0, ptr %v21, align 245 %v22 = add nuw nsw i32 %v0, 146 %v23 = icmp eq i32 %v22, 647 br i1 %v23, label %b2, label %b148 49b2: ; preds = %b150 ret void51}52 53attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-length64b,+hvxv60" }54