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1; RUN: llc -mtriple=hexagon -enable-pipeliner < %s2; REQUIRES: asserts3 4; Check that we correctly rename instructions that use a Phi's loop value,5; and the Phi and loop value are defined after the instruction.6 7%s.0 = type { [4 x i8], i16, i16, i32, [8 x i8], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [4 x %s.1], [4 x i8], i32, i32, [4 x i8], [14 x %s.2] }8%s.1 = type { i32, i32 }9%s.2 = type { [4 x i8] }10 11; Function Attrs: nounwind12define void @f0(ptr nocapture %a0) #0 {13b0:14 br i1 undef, label %b1, label %b215 16b1: ; preds = %b017 unreachable18 19b2: ; preds = %b020 br label %b821 22b3: ; preds = %b923 unreachable24 25b4: ; preds = %b926 br i1 undef, label %b7, label %b527 28b5: ; preds = %b429 br i1 undef, label %b6, label %b730 31b6: ; preds = %b6, %b532 %v0 = phi i32 [ %v10, %b6 ], [ 0, %b5 ]33 %v1 = load i32, ptr undef, align 434 %v2 = getelementptr inbounds %s.0, ptr %a0, i32 0, i32 29, i32 %v035 %v4 = load i32, ptr %v2, align 436 %v5 = and i32 %v1, 6553537 %v6 = and i32 %v4, -6553638 %v7 = or i32 %v6, %v539 %v8 = and i32 %v7, -203161740 %v9 = or i32 %v8, 041 store i32 %v9, ptr %v2, align 442 %v10 = add nsw i32 %v0, 143 %v11 = icmp eq i32 %v10, undef44 br i1 %v11, label %b7, label %b645 46b7: ; preds = %b6, %b5, %b447 ret void48 49b8: ; preds = %b8, %b250 br i1 undef, label %b9, label %b851 52b9: ; preds = %b853 br i1 undef, label %b3, label %b454}55 56attributes #0 = { nounwind "target-cpu"="hexagonv55" }57