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1; RUN: llc -mtriple=hexagon --enable-pipeliner -hexagon-expand-condsets=0 < %s2; REQUIRES: asserts3 4; Disable expand-condsets because it will assert on undefined registers.5 6define void @f0() #0 {7b0:8 br i1 undef, label %b1, label %b29 10b1: ; preds = %b011 unreachable12 13b2: ; preds = %b014 br i1 undef, label %b3, label %b415 16b3: ; preds = %b3, %b217 br i1 undef, label %b4, label %b318 19b4: ; preds = %b3, %b220 %v0 = ashr i32 undef, 2521 %v1 = mul nsw i32 %v0, 222 %v2 = load i8, ptr undef, align 123 br i1 undef, label %b5, label %b1024 25b5: ; preds = %b426 br i1 undef, label %b6, label %b927 28b6: ; preds = %b529 br label %b730 31b7: ; preds = %b7, %b632 br i1 undef, label %b7, label %b833 34b8: ; preds = %b735 br i1 undef, label %b10, label %b936 37b9: ; preds = %b9, %b8, %b538 %v3 = phi i8 [ %v7, %b9 ], [ undef, %b8 ], [ %v2, %b5 ]39 %v4 = phi i32 [ %v8, %b9 ], [ undef, %b8 ], [ 1, %b5 ]40 %v5 = add i32 %v4, undef41 %v6 = load i8, ptr undef, align 142 %v7 = select i1 undef, i8 %v6, i8 %v343 %v8 = add nsw i32 %v4, 144 %v9 = icmp eq i32 %v8, %v145 br i1 %v9, label %b10, label %b946 47b10: ; preds = %b9, %b8, %b448 %v10 = phi i8 [ %v2, %b4 ], [ undef, %b8 ], [ %v7, %b9 ]49 br i1 false, label %b11, label %b1250 51b11: ; preds = %b1052 unreachable53 54b12: ; preds = %b1055 br label %b1356 57b13: ; preds = %b13, %b1258 br label %b1359}60 61attributes #0 = { nounwind "target-cpu"="hexagonv55" }62