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1# RUN: llc -mtriple=hexagon -run-pass pipeliner -debug-only=pipeliner %s -o /dev/null 2>&1 | FileCheck %s2# REQUIRES: asserts3 4# Test that there are no loop-carried dependencies between all memory instructions.5 6# CHECK: SU(0): %8:intregs = PHI %1:intregs, %bb.1, %9:intregs, %bb.27# CHECK-NEXT: # preds left8# CHECK-NEXT: # succs left9# CHECK-NEXT: # rdefs left10# CHECK-NEXT: Latency11# CHECK-NEXT: Depth12# CHECK-NEXT: Height13# CHECK-NEXT: Successors:14# CHECK-DAG: SU(6): Data Latency=0 Reg=%815# CHECK-DAG: SU(5): Data Latency=0 Reg=%816# CHECK-DAG: SU(3): Data Latency=0 Reg=%817# CHECK-DAG: SU(6): Anti Latency=118# CHECK-NEXT: SU(1): %10:intregs = PHI %2:intregs, %bb.1, %11:intregs, %bb.219# CHECK-NEXT: # preds left20# CHECK-NEXT: # succs left21# CHECK-NEXT: # rdefs left22# CHECK-NEXT: Latency23# CHECK-NEXT: Depth24# CHECK-NEXT: Height25# CHECK-NEXT: Successors:26# CHECK-DAG: SU(7): Data Latency=0 Reg=%1027# CHECK-DAG: SU(4): Data Latency=0 Reg=%1028# CHECK-DAG: SU(2): Data Latency=0 Reg=%1029# CHECK-DAG: SU(7): Anti Latency=130# CHECK-NEXT: SU(2): %12:hvxvr = V6_vL32b_ai %10:intregs, 0 :: (load (s1024) from %ir.iptr.09, !tbaa !4)31# CHECK-NEXT: # preds left32# CHECK-NEXT: # succs left33# CHECK-NEXT: # rdefs left34# CHECK-NEXT: Latency35# CHECK-NEXT: Depth36# CHECK-NEXT: Height37# CHECK-NEXT: Predecessors:38# CHECK-NEXT: SU(1): Data Latency=0 Reg=%1039# CHECK-NEXT: Successors:40# CHECK-NEXT: SU(3): Data Latency=0 Reg=%1241# CHECK-NEXT: SU(3): V6_vS32b_ai %8:intregs, 0, %12:hvxvr :: (store (s1024) into %ir.optr.010, !tbaa !4)42# CHECK-NEXT: # preds left43# CHECK-NEXT: # succs left44# CHECK-NEXT: # rdefs left45# CHECK-NEXT: Latency46# CHECK-NEXT: Depth47# CHECK-NEXT: Height48# CHECK-NEXT: Predecessors:49# CHECK-DAG: SU(2): Data Latency=0 Reg=%1250# CHECK-DAG: SU(0): Data Latency=0 Reg=%851# CHECK-NEXT: SU(4): %13:hvxvr = V6_vL32b_ai %10:intregs, 128 :: (load (s1024) from %ir.cgep, !tbaa !4)52# CHECK-NEXT: # preds left53# CHECK-NEXT: # succs left54# CHECK-NEXT: # rdefs left55# CHECK-NEXT: Latency56# CHECK-NEXT: Depth57# CHECK-NEXT: Height58# CHECK-NEXT: Predecessors:59# CHECK-NEXT: SU(1): Data Latency=0 Reg=%1060# CHECK-NEXT: Successors:61# CHECK-NEXT: SU(5): Data Latency=0 Reg=%1362# CHECK-NEXT: SU(5): V6_vS32b_ai %8:intregs, 128, %13:hvxvr :: (store (s1024) into %ir.cgep3, !tbaa !4)63 64 65 66 67--- |68 define dso_local void @foo(ptr noundef readonly captures(none) %in, ptr noalias noundef writeonly captures(none) %out, i32 noundef %width) local_unnamed_addr #0 {69 entry:70 %cmp7 = icmp sgt i32 %width, 071 br i1 %cmp7, label %for.body.preheader, label %for.end72 73 for.body.preheader: ; preds = %entry74 %0 = add i32 %width, 12875 br label %for.body76 77 for.body: ; preds = %for.body.preheader, %for.body78 %lsr.iv = phi i32 [ %0, %for.body.preheader ], [ %lsr.iv.next, %for.body ]79 %optr.010 = phi ptr [ %cgep4, %for.body ], [ %out, %for.body.preheader ]80 %iptr.09 = phi ptr [ %cgep5, %for.body ], [ %in, %for.body.preheader ]81 %ald = load <128 x i8>, ptr %iptr.09, align 128, !tbaa !482 %cst = bitcast <128 x i8> %ald to <32 x i32>83 store <32 x i32> %cst, ptr %optr.010, align 128, !tbaa !484 %cgep = getelementptr i8, ptr %iptr.09, i32 12885 %ald1 = load <128 x i8>, ptr %cgep, align 128, !tbaa !486 %cst2 = bitcast <128 x i8> %ald1 to <32 x i32>87 %cgep3 = getelementptr i8, ptr %optr.010, i32 12888 store <32 x i32> %cst2, ptr %cgep3, align 128, !tbaa !489 %lsr.iv.next = add i32 %lsr.iv, -12890 %cmp = icmp samesign ugt i32 %lsr.iv.next, 12891 %cgep4 = getelementptr i8, ptr %optr.010, i32 25692 %cgep5 = getelementptr i8, ptr %iptr.09, i32 25693 br i1 %cmp, label %for.body, label %for.end94 95 for.end: ; preds = %for.body, %entry96 ret void97 }98 99 attributes #0 = { "target-cpu"="hexagonv60" "target-features"="+hvx-length128b,+hvxv69,+v66,-long-calls" }100 101 !llvm.module.flags = !{!0, !1, !2, !3}102 103 !0 = !{i32 1, !"wchar_size", i32 4}104 !1 = !{i32 8, !"PIC Level", i32 2}105 !2 = !{i32 7, !"PIE Level", i32 2}106 !3 = !{i32 7, !"frame-pointer", i32 2}107 !4 = !{!5, !5, i64 0}108 !5 = !{!"omnipotent char", !6, i64 0}109 !6 = !{!"Simple C/C++ TBAA"}110...111---112name: foo113tracksRegLiveness: true114body: |115 bb.0.entry:116 successors: %bb.1(0x50000000), %bb.3(0x30000000)117 liveins: $r0, $r1, $r2118 119 %9:intregs = COPY $r2120 %8:intregs = COPY $r1121 %7:intregs = COPY $r0122 %10:predregs = C2_cmpgti %9, 0123 J2_jumpf %10, %bb.3, implicit-def dead $pc124 J2_jump %bb.1, implicit-def dead $pc125 126 bb.1.for.body.preheader:127 successors: %bb.2(0x80000000)128 129 %0:intregs = A2_addi %9, 128130 %15:intregs = A2_addi %0, -1131 %16:intregs = S2_lsr_i_r %15, 7132 %17:intregs = COPY %16133 J2_loop0r %bb.2, %17, implicit-def $lc0, implicit-def $sa0, implicit-def $usr134 135 bb.2.for.body (machine-block-address-taken):136 successors: %bb.2(0x7c000000), %bb.3(0x04000000)137 138 %2:intregs = PHI %8, %bb.1, %5, %bb.2139 %3:intregs = PHI %7, %bb.1, %6, %bb.2140 %12:hvxvr = V6_vL32b_ai %3, 0 :: (load (s1024) from %ir.iptr.09, !tbaa !4)141 V6_vS32b_ai %2, 0, killed %12 :: (store (s1024) into %ir.optr.010, !tbaa !4)142 %13:hvxvr = V6_vL32b_ai %3, 128 :: (load (s1024) from %ir.cgep, !tbaa !4)143 V6_vS32b_ai %2, 128, killed %13 :: (store (s1024) into %ir.cgep3, !tbaa !4)144 %5:intregs = A2_addi %2, 256145 %6:intregs = A2_addi %3, 256146 ENDLOOP0 %bb.2, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0147 J2_jump %bb.3, implicit-def dead $pc148 149 bb.3.for.end:150 PS_jmpret $r31, implicit-def dead $pc151...152