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1; RUN: llc -mtriple=hexagon -enable-pipeliner < %s2; REQUIRES: asserts3 4; Test that we include all the nodes in the final node ordering5; computation. This test creates two set of nodes that are processed6; by computeNodeOrder().7 8; Function Attrs: nounwind9define void @f0(i32 %a0) #0 {10b0:11 %v0 = add nsw i32 undef, 412 %v1 = ashr i32 %a0, 113 br label %b114 15b1: ; preds = %b1, %b016 %v2 = phi i64 [ %v5, %b1 ], [ 0, %b0 ]17 %v3 = phi i64 [ %v9, %b1 ], [ undef, %b0 ]18 %v4 = phi i32 [ %v10, %b1 ], [ 0, %b0 ]19 %v5 = tail call i64 @llvm.hexagon.M2.vdmacs.s0(i64 %v2, i64 %v3, i64 undef)20 %v6 = tail call i64 @llvm.hexagon.A2.combinew(i32 0, i32 0)21 %v7 = tail call i64 @llvm.hexagon.S2.shuffeh(i64 %v6, i64 undef)22 %v8 = trunc i64 %v7 to i3223 %v9 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v8, i32 undef)24 %v10 = add nsw i32 %v4, 125 %v11 = icmp eq i32 %v10, %v126 br i1 %v11, label %b2, label %b127 28b2: ; preds = %b129 %v12 = trunc i64 %v5 to i3230 %v13 = inttoptr i32 %v0 to ptr31 store i32 %v12, ptr %v13, align 4, !tbaa !032 call void @llvm.trap()33 unreachable34}35 36; Function Attrs: nounwind readnone37declare i64 @llvm.hexagon.A2.combinew(i32, i32) #138 39; Function Attrs: nounwind readnone40declare i64 @llvm.hexagon.M2.vdmacs.s0(i64, i64, i64) #141 42; Function Attrs: nounwind readnone43declare i64 @llvm.hexagon.S2.shuffeh(i64, i64) #144 45; Function Attrs: noreturn nounwind46declare void @llvm.trap() #247 48attributes #0 = { nounwind "target-cpu"="hexagonv55" }49attributes #1 = { nounwind readnone }50attributes #2 = { noreturn nounwind }51 52!0 = !{!1, !1, i64 0}53!1 = !{!"int", !2}54!2 = !{!"omnipotent char", !3}55!3 = !{!"Simple C/C++ TBAA"}56