84 lines · plain
1; RUN: llc -mtriple=hexagon < %s2; REQUIRES: asserts3 4; Test that we order instruction within a packet correctly. In this case,5; we added a definition of a value after the use in a packet, which6; caused an assert.7 8define void @f0(i32 %a0) {9b0:10 %v0 = ashr i32 %a0, 111 br i1 undef, label %b3, label %b112 13b1: ; preds = %b1, %b014 %v1 = phi i32 [ %v23, %b1 ], [ undef, %b0 ]15 %v2 = phi i64 [ %v14, %b1 ], [ 0, %b0 ]16 %v3 = phi i64 [ %v11, %b1 ], [ 0, %b0 ]17 %v4 = phi i32 [ %v25, %b1 ], [ 0, %b0 ]18 %v5 = phi i32 [ %v6, %b1 ], [ undef, %b0 ]19 %v6 = phi i32 [ %v20, %b1 ], [ undef, %b0 ]20 %v7 = phi i32 [ %v24, %b1 ], [ undef, %b0 ]21 %v8 = tail call i32 @llvm.hexagon.A2.combine.lh(i32 %v6, i32 %v5)22 %v9 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v8, i32 undef)23 %v10 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v1, i32 undef)24 %v11 = tail call i64 @llvm.hexagon.M2.vdmacs.s0(i64 %v3, i64 %v9, i64 undef)25 %v12 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v5, i32 %v5)26 %v13 = tail call i64 @llvm.hexagon.S2.valignib(i64 %v10, i64 undef, i32 2)27 %v14 = tail call i64 @llvm.hexagon.M2.vdmacs.s0(i64 %v2, i64 %v12, i64 %v13)28 %v15 = inttoptr i32 %v7 to ptr29 %v16 = load i16, ptr %v15, align 230 %v17 = sext i16 %v16 to i3231 %v18 = add nsw i32 %v7, -832 %v19 = tail call i64 @llvm.hexagon.M2.vdmacs.s0(i64 undef, i64 %v12, i64 0)33 %v20 = tail call i32 @llvm.hexagon.A2.combine.ll(i32 %v17, i32 %v1)34 %v21 = inttoptr i32 %v18 to ptr35 %v22 = load i16, ptr %v21, align 236 %v23 = sext i16 %v22 to i3237 %v24 = add nsw i32 %v7, -1638 %v25 = add nsw i32 %v4, 139 %v26 = icmp eq i32 %v25, %v040 br i1 %v26, label %b2, label %b141 42b2: ; preds = %b143 %v27 = phi i64 [ %v19, %b1 ]44 %v28 = phi i64 [ %v14, %b1 ]45 %v29 = phi i64 [ %v11, %b1 ]46 %v30 = trunc i64 %v27 to i3247 %v31 = trunc i64 %v28 to i3248 %v32 = lshr i64 %v29, 3249 %v33 = trunc i64 %v32 to i3250 br label %b351 52b3: ; preds = %b2, %b053 %v34 = phi i32 [ %v30, %b2 ], [ undef, %b0 ]54 %v35 = phi i32 [ %v31, %b2 ], [ undef, %b0 ]55 %v36 = phi i32 [ %v33, %b2 ], [ undef, %b0 ]56 store i32 %v35, ptr undef, align 457 %v38 = getelementptr inbounds i8, ptr null, i32 858 store i32 %v34, ptr %v38, align 459 store i32 %v36, ptr undef, align 460 call void @llvm.trap()61 unreachable62}63 64; Function Attrs: nounwind readnone65declare i32 @llvm.hexagon.A2.combine.ll(i32, i32) #066 67; Function Attrs: nounwind readnone68declare i64 @llvm.hexagon.A2.combinew(i32, i32) #069 70; Function Attrs: nounwind readnone71declare i64 @llvm.hexagon.M2.vdmacs.s0(i64, i64, i64) #072 73; Function Attrs: nounwind readnone74declare i32 @llvm.hexagon.A2.combine.lh(i32, i32) #075 76; Function Attrs: nounwind readnone77declare i64 @llvm.hexagon.S2.valignib(i64, i64, i32) #078 79; Function Attrs: noreturn nounwind80declare void @llvm.trap() #181 82attributes #0 = { nounwind readnone }83attributes #1 = { noreturn nounwind }84