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1; RUN: llc -mtriple=hexagon < %s -pipeliner-experimental-cg=true -terminal-rule=0 | FileCheck %s2 3; Test that the instruction ordering code in the pipeliner fixes up dependences4; between post-increment register definitions and uses so that the register5; allocator does not allocate an additional register. The following test case6; should generate a single packet.7 8; CHECK: loop0(.LBB0_[[LOOP:.]],9; CHECK: .LBB0_[[LOOP]]:10; CHECK: {11; CHECK-NOT: {12; CHECK: :endloop013 14define void @test(ptr nocapture %v1, i64 %v2, i32 %len) local_unnamed_addr #0 {15entry:16 %cmp7 = icmp sgt i32 %len, 017 br i1 %cmp7, label %for.body, label %for.end18 19for.body:20 %arrayidx.phi = phi ptr [ %arrayidx.inc, %for.body ], [ %v1, %entry ]21 %i.08 = phi i32 [ %inc, %for.body ], [ 0, %entry ]22 %0 = load i64, ptr %arrayidx.phi, align 823 %1 = tail call i64 @llvm.hexagon.M2.mmpyul.rs1(i64 %0, i64 %v2)24 store i64 %1, ptr %arrayidx.phi, align 825 %inc = add nuw nsw i32 %i.08, 126 %exitcond = icmp eq i32 %inc, %len27 %arrayidx.inc = getelementptr i64, ptr %arrayidx.phi, i32 128 br i1 %exitcond, label %for.end, label %for.body29 30for.end:31 ret void32}33 34declare i64 @llvm.hexagon.M2.mmpyul.rs1(i64, i64) #135 36attributes #0 = { nounwind "target-cpu"="hexagonv60" }37attributes #1 = { nounwind readnone }38