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1; RUN: llc -mtriple=hexagon -enable-pipeliner < %s2; REQUIRES: asserts3 4; Check that the dependences are order correctly, and the list can be5; updated when the instruction to insert has a def and use conflict.6 7; Function Attrs: nounwind8define fastcc void @f0() #0 {9b0:10 br i1 undef, label %b7, label %b111 12b1: ; preds = %b013 br i1 undef, label %b2, label %b414 15b2: ; preds = %b116 %v0 = load i16, ptr undef, align 217 br label %b518 19b3: ; preds = %b520 br label %b421 22b4: ; preds = %b3, %b123 %v1 = phi i16 [ %v11, %b3 ], [ 0, %b1 ]24 br i1 false, label %b7, label %b625 26b5: ; preds = %b5, %b227 %v2 = phi i16 [ %v3, %b5 ], [ undef, %b2 ]28 %v3 = phi i16 [ 0, %b5 ], [ %v0, %b2 ]29 %v4 = phi i16 [ %v2, %b5 ], [ undef, %b2 ]30 %v5 = phi i16 [ %v11, %b5 ], [ 0, %b2 ]31 %v6 = phi i32 [ %v12, %b5 ], [ undef, %b2 ]32 %v7 = or i16 0, %v533 %v8 = lshr i16 %v4, 834 %v9 = or i16 %v8, %v735 %v10 = or i16 0, %v936 %v11 = or i16 0, %v1037 %v12 = add nsw i32 %v6, -3238 %v13 = icmp sgt i32 %v12, 3139 br i1 %v13, label %b5, label %b340 41b6: ; preds = %b442 br label %b743 44b7: ; preds = %b6, %b4, %b045 ret void46}47 48attributes #0 = { nounwind "target-cpu"="hexagonv55" }49